Readout electronics for low occupancy High-Pressure Gas TPCs

TL;DR

The paper addresses the high cost of readout electronics for high-pressure gas TPCs by proposing a scalable FPGA-based solution optimized for the DUNE ND-GAr. It validates the approach using the TOAD test stand with an ALICE MWPC OROC, demonstrating readout of around 10k channels up to 4.5 barA and integrating with the DUNE DAQ software. Key findings include low noise levels with identifiable DC/DC-induced noise and the need for improved cooling and grounding for full deployment, along with a clear path to cost-effective scaling. The work suggests that HPgTPC readout can meet physics needs at a fraction of collider-based systems, potentially enabling a magnetised HPgTPC in DUNE at substantially reduced cost.

Abstract

HPgTPCs have benefits such as low energy threshold, magnetisability, and 4$π$ acceptance, making them ideal for neutrino experiments such as DUNE. We present the design of an FPGA-based solution optimised for ND-GAr, which is part of the Phase-II more capable near detector for DUNE. These electronics reduce the cost significantly compared to using collider readout electronics which are typically designed for much higher occupancy and therefore, for example, need much larger numbers of FPGAs and power per channel. We demonstrate the performance of our electronics with the TOAD at Fermilab in the US at a range of pressures and gas mixtures up to 4.5barA, reading out ~10000 channels from a multi-wire proportional chamber. The operation took place between April and July of 2024. We measure the noise characteristics of the system to be sufficiently low and we identify sources of noise that can be further mitigated in the next iteration. We also note that the cooling scheme used in the test requires improvement before full-scale deployment. Despite these necessary improvements, we show that the system can fulfil the needs of a HPgTPC for a fraction of the price of collider readout electronics.

Figures (16)

• Figure 1: The TOAD pressure vessel in the test environment at Fermilab. Around the vessel, the hydraulic pressure clamps can be seen. In the centre, there is access to five flanges, which are unused in TOAD but previously used for mounting an optical readout system. The KF40 feedthroughs that are used for data readout and CCM via the blue cables are labelled. Various other KF40 and KF25 flanges on the vessel provide access for the different subsystems, but cannot be seen in this image. The gas and evacuation system is to the right of the vessel.
• Figure 2: ND-GAr readout scheme with direct power provided to all DAQ cards and explicit timing signal distribution. The vertical, dark green line represents the ALICE Inner/Outer Readout Chamber. The orange boxes represent COTS network switches.
• Figure 3: FEC board hosting two daisy-chained SAMPA chips designed for the TOAD OROC based test beam readout.
• Figure 4: PAT card top-level image, on the top the two DC/DC converters can be seen, one dedicated for the main voltage translation (Main DC/DC) and the second one for the FEC power (FEC DC/DC). The FPGA position is on the back side of the board at the position indicated, the FEC communication is organised in groups of IDC connectors shown with the white box on the left. Finally, there are four placeholders for clock synthesizers, however, only two are mounted, with one of them indicated by the white arrow on the right.
• Figure 5: Diagram of the firmware schematic. The black lines show the data path, through successive levels of buffering (L0, L1, L2), format conversions and the RR data flow management scheme. The green lines show the clock distribution (derived from the DUNE Timing System). The orange lines show telemetry signals to/from internal/external components and the CCM system. The thicker arrows denote serial communication to other boards or switches in the system.