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VeriRAG: A Retrieval-Augmented Framework for Automated RTL Testability Repair

Haomin Qi, Yuyang Du, Lihao Zhang, Soung Chang Liew, Kexin Chen, Yining Du

TL;DR

VeriRAG tackles RTL design-for-testability repair by integrating a retrieval-augmented generation pipeline with a structure-aware autoencoder to fetch validated RTL references from VeriDFT. The LLM then performs iterative, compiler-guided revisions to eliminate DFT violations while preserving synthesizability and logical equivalence, with a final logic equivalence check. Across multiple LLMs and ablations, VeriRAG delivers substantial gains over zero-shot baselines, including a 7.72x improvement for GPT-o1, and demonstrates the critical value of structure-aware retrieval and iterative feedback. The work introduces VeriDFT and an open-source VeriRAG workflow, setting a foundation for automated, DFT-aware RTL repair in practical CAD environments.

Abstract

Large language models (LLMs) have demonstrated immense potential in computer-aided design (CAD), particularly for automated debugging and verification within electronic design automation (EDA) tools. However, Design for Testability (DFT) remains a relatively underexplored area. This paper presents VeriRAG, the first LLM-assisted DFT-EDA framework. VeriRAG leverages a Retrieval-Augmented Generation (RAG) approach to enable LLM to revise code to ensure DFT compliance. VeriRAG integrates (1) an autoencoder-based similarity measurement model for precise retrieval of reference RTL designs for the LLM, and (2) an iterative code revision pipeline that allows the LLM to ensure DFT compliance while maintaining synthesizability. To support VeriRAG, we introduce VeriDFT, a Verilog-based DFT dataset curated for DFT-aware RTL repairs. VeriRAG retrieves structurally similar RTL designs from VeriDFT, each paired with a rigorously validated correction, as references for code repair. With VeriRAG and VeriDFT, we achieve fully automated DFT correction -- resulting in a 7.72-fold improvement in successful repair rate compared to the zero-shot baseline (Fig. 5 in Section V). Ablation studies further confirm the contribution of each component of the VeriRAG framework. We open-source our data, models, and scripts at https://github.com/yuyangdu01/LLM4DFT.

VeriRAG: A Retrieval-Augmented Framework for Automated RTL Testability Repair

TL;DR

VeriRAG tackles RTL design-for-testability repair by integrating a retrieval-augmented generation pipeline with a structure-aware autoencoder to fetch validated RTL references from VeriDFT. The LLM then performs iterative, compiler-guided revisions to eliminate DFT violations while preserving synthesizability and logical equivalence, with a final logic equivalence check. Across multiple LLMs and ablations, VeriRAG delivers substantial gains over zero-shot baselines, including a 7.72x improvement for GPT-o1, and demonstrates the critical value of structure-aware retrieval and iterative feedback. The work introduces VeriDFT and an open-source VeriRAG workflow, setting a foundation for automated, DFT-aware RTL repair in practical CAD environments.

Abstract

Large language models (LLMs) have demonstrated immense potential in computer-aided design (CAD), particularly for automated debugging and verification within electronic design automation (EDA) tools. However, Design for Testability (DFT) remains a relatively underexplored area. This paper presents VeriRAG, the first LLM-assisted DFT-EDA framework. VeriRAG leverages a Retrieval-Augmented Generation (RAG) approach to enable LLM to revise code to ensure DFT compliance. VeriRAG integrates (1) an autoencoder-based similarity measurement model for precise retrieval of reference RTL designs for the LLM, and (2) an iterative code revision pipeline that allows the LLM to ensure DFT compliance while maintaining synthesizability. To support VeriRAG, we introduce VeriDFT, a Verilog-based DFT dataset curated for DFT-aware RTL repairs. VeriRAG retrieves structurally similar RTL designs from VeriDFT, each paired with a rigorously validated correction, as references for code repair. With VeriRAG and VeriDFT, we achieve fully automated DFT correction -- resulting in a 7.72-fold improvement in successful repair rate compared to the zero-shot baseline (Fig. 5 in Section V). Ablation studies further confirm the contribution of each component of the VeriRAG framework. We open-source our data, models, and scripts at https://github.com/yuyangdu01/LLM4DFT.

Paper Structure

This paper contains 14 sections, 6 equations, 5 figures.

Table of Contents

  1. Introduction
  2. Background and Related Works
  3. LLM for CAD
  4. DFT at RTL level
  5. RAG for RTL design
  6. Deep Learning for Hardware and DFT Error Analysis
  7. The VeriDFT Dataset
  8. Data Cleaning and Data partition
  9. Verilog-JSON Conversion to Capture Hardware Similarity
  10. Methodology
  11. Training Autoencoder Network
  12. Application of VeriRAG framework
  13. Experiments
  14. Conclusions and Outlook

Figures (5)

  • Figure 1: Statistic overview of the VeriDFT dataset: (a) proportion of DFT-related error types, and (b) code length distribution histogram.
  • Figure 2: Verilog-to-JSON transformation: (a) circuit diagram; (b) corresponding RTL implementation; (c) detailed netlist with low-level look up table (LUT) implementation (a distraction for similarity measurement); (d) JSON representation generated by Yosys capturing topological connections between major logic gates and sequential elements. In this work, “hardware structure” refers to these gate-level topologies, reflecting the structural context critical to DFT error patterns.
  • Figure 3: The VeriRAG framework -- (a) training of autoencoder network, (b) RAG-based code revision pipeline in the testing process.
  • Figure 4: Success rates of preliminary DFT error corrections (without considering logical equivalence) for different LLMs and ablation cases tested.
  • Figure 5: Ultimate code revision success rates (with logical equivalence) for different LLMs and ablation cases tested.