The New LLM Bottleneck: A Systems Perspective on Latent Attention and Mixture-of-Experts
Sungmin Yun, Seonyong Park, Hwayong Nam, Younjoo Lee, Gunjun Lee, Kwanhee Kyung, Sangpyo Kim, Nam Sung Kim, Jongmin Kim, Hyungyo Kim, Juhwan Cho, Seungmin Baek, Jung Ho Ahn
TL;DR
This paper reframes LLM performance bottlenecks by showing that Multi-head Latent Attention (MLA) and Mixture-of-Experts (MoE) move the bottleneck away from memory-bound attention toward compute-bound or balanced regimes, enabling larger batch sizes during inference.It demonstrates that MLA reduces KV cache size via latent compression and can be ordered to boost data reuse, while MoE scales capacity through sparse routing, requiring large batches to saturate accelerators.An end-to-end analysis of serving systems reveals that high-bandwidth interconnects and data/ expert parallelism are essential to exploit MLA/MoE synergy and meet SLOs, with practical guidance on when to deploy DP versus TP and how to scale across accelerators.Together, these findings argue for a system-centric design methodology that emphasizes compute/memory balance and interconnects over specialized attention hardware.
Abstract
Computational workloads composing traditional Transformer models are starkly bifurcated. Multi-Head Attention (MHA) is memory-bound, with low arithmetic intensity, while feedforward layers are compute-bound. This dichotomy has long motivated research into specialized hardware to mitigate the MHA bottleneck. This paper argues that recent architectural shifts, namely Multi-head Latent Attention (MLA) and Mixture-of-Experts (MoE), challenge the premise of specialized attention hardware. We make two key observations. First, the arithmetic intensity of MLA is over two orders of magnitude greater than that of MHA, shifting it close to a compute-bound regime well-suited for modern accelerators like GPUs. Second, by distributing MoE experts across a pool of accelerators, their arithmetic intensity can be tuned through batching to match that of the dense layers, creating a more balanced computational profile. These findings reveal a diminishing need for specialized attention hardware. The central challenge for next-generation Transformers is no longer accelerating a single memory-bound layer. Instead, the focus must shift to designing balanced systems with sufficient compute, memory capacity, memory bandwidth, and high-bandwidth interconnects to manage the diverse demands of large-scale models.
