A superinductor in a deep sub-micron integrated circuit

TL;DR

This work demonstrates a silicon CMOS superinductor by leveraging the kinetic inductance of TiN thin films in a 22-nm process, achieving $L_K$-based inductors that are orders of magnitude more compact than conventional CMOS inductors. By integrating these superinductors with a silicon SET on the same IC, the authors realize an rfSET with substantially reduced parasitics and more than a two-orders-of-magnitude improvement in sensitivity, coupled with a 10,000× area reduction. The readout reaches exceptionally low minimum integration times, with $t_{min}$ as low as $1 \pm 0.3$ ps at high rf powers due to non-linear kinetic inductance, enabling rapid, quantum-limited sensing for semiconductor spin qubits and potential applications in detector arrays and quantum simulations. Overall, the work points to scalable, dense, cryogenic silicon-based quantum sensors and readout infrastructure enabled by monolithic superconducting elements in standard silicon ICs.

Abstract

Superinductors are circuit elements characterised by an intrinsic impedance in excess of the superconducting resistance quantum ($R_\text{Q}\approx6.45~$k$Ω$), with applications from metrology and sensing to quantum computing. However, they are typically obtained using exotic materials with high density inductance such as Josephson junctions, superconducting nanowires or twisted two-dimensional materials. Here, we present a superinductor realised within a silicon integrated circuit (IC), exploiting the high kinetic inductance ($\sim 1$~nH/$\square$) of TiN thin films native to the manufacturing process (22-nm FDSOI). By interfacing the superinductor to a silicon quantum dot formed within the same IC, we demonstrate a radio-frequency single-electron transistor (rfSET), the most widely used sensor in semiconductor-based quantum computers. The integrated nature of the rfSET reduces its parasitics which, together with the high impedance, yields a sensitivity improvement of more than two orders of magnitude over the state-of-the-art, combined with a 10,000-fold area reduction. Beyond providing the basis for dense arrays of integrated and high-performance qubit sensors, the realization of high-kinetic-inductance superconducting devices integrated within modern silicon ICs opens many opportunities, including kinetic-inductance detector arrays for astronomy and the study of metamaterials and quantum simulators based on 1D and 2D resonator arrays.

Figures (4)

• Figure 1: A titanium nitride CMOS superinductor. (a) 22-nm CMOS chip diagram with insets showing sizes of the spiral inductor and TiN thin film superinductor. (b) Four point I-V curve for different temperatures for Type B superconducting TiN thin film, with the inset showing the resistance vs temperature for both Type A and Type B thin film types, normalized to the maximum resistance of Type A. (c) S$_{11}$ measurement of the resonant circuit shown in the inset, for the superconducting (green) and normal (blue) states of the film, the latter achieved using an rf power above the critical rf power.
• Figure 2: Parametric characterisation. (a) Dependence of kinetic inductance on temperature for TiN thin films of Type A (red, one device) and Type B (orange, three devices) with a fit to Eq. 1. For Type A: (b) magnetic field dependence of kinetic inductance for different mixing chamber temperatures and (c) & (d) kinetic inductance as a function of dc current (rf power) for different rf powers (dc currents).
• Figure 3: Integrated rfSET. (a) Circuit schematic including the rf source, coupling capacitor $C_c$, kinetic inductor $L_K$, equivalent resonator capacitance $C$ and field-effect transistor used to form the SET. Inset) Schematic cross-section of the SET showing a charged island at the Si/SiO$_2$ interface directly under the gate as well as the flow of the single-electron AC current (red arrows). (b) $S_{11}$ magnitude and phase of the resonant circuit as a function of the gate voltage of the SET demonstrating the sensitivity to changes in the SET resistance. (c) Magnitude of the reflected rf signal (top) and drain current (bottom) as a function of the gate-source and drain-source voltage, showing regions of charge stability, i.e. Coulomb diamonds. The labels indicate the charge configuration where $N$ indicates a discrete charge offset. The positive slope features inside the conductive regions are associated to 1d density of states in the SD contacts.
• Figure 4: Sensitivity benchmark. (a) Plot of the magnitude of the reflected signal versus gate-source voltage for the Coulomb peak used in the sensitivity benchmark. Inset) Plot in the IQ plane of 1 $\mu$s time traces at the top (green) and bottom (blue) of the Coulomb peak using an integration time of 4 ns. (b) SNR vs integration time for different rf powers with linear fits extrapolating to SNR = 1. (c) Minimum integration time as a function of applied rf power with fits to the low power (blue) and high power (green) shown by the dashed lines. (d) $S_{11}$ measurement of the resonant circuit versus frequency and power showing a resonance frequency reduction as the power is increased due to the non-linear behaviour of the TiN inductance. At even higher powers, the resonator becomes normal.