Compilation of QCrank Encoding Algorithm for a Dynamically Programmable Qubit Array Processor

TL;DR

The paper addresses hardware-aware compilation for dynamically programmable qubit arrays (DPQAs) by evaluating QCrank, a real-valued data encoding protocol, under a realistic Pauli-noise model implemented in Qiskit. It demonstrates that QCrank can store $L = n_d \cdot 2^{n_a}$ real numbers on $n_a+n_d$ qubits using uniformly controlled rotations and CZ gates, with the DPQA's reconfigurable connectivity enabling high parallelism and favorable scaling. Through simulations and comparisons to H1-1E and IBM Fez, the work shows competitive accuracy that benefits from parallel global gates and strategic atom movement, while calibrations and post-processing can recover dynamic range. The study provides concrete compiler design principles for DPQAs, discusses noise-mitigation opportunities (e.g., randomized compiling), and outlines future directions toward multi-zone layouts and more refined noise models to further improve fidelity.

Abstract

Algorithm and hardware-aware compilation co-design is essential for the efficient deployment of near-term quantum programs. We present a compilation case-study implementing QCrank -- an efficient encoding protocol for storing sequenced real-valued classical data in a quantum state -- targeting neutral atom-based Dynamically Programmable Qubit Arrays (DPQAs). We show how key features of neutral-atom arrays such as high qubits count, operation parallelism, multi-zone architecture, and natively reconfigurable connectivity can be used to inform effective algorithm deployment. We identify algorithmic and circuit features that signal opportunities to implement them in a hardware-efficient manner. To evaluate projected hardware performance, we define a realistic noise model for DPQAs using parameterized Pauli channels, implement it in Qiskit circuit simulators, and assess QCrank's accuracy for writing and reading back 24-320 real numbers into 6-20 qubits. We compare DPQA results with simulated performances of Quantinuum's H1-1E and with experimental results from IBM Fez, highlighting promising accuracy scaling for DPQAs.

Figures (5)

• Figure 1: Full QCrank circuit for 2 address ($\boldsymbol{a_i}$) and 4 data ($\boldsymbol{d_j}$) qubits with storage capacity of 16 real values. (a) originally circuit proposed in Ref. qcrank-nature, (b) Equivalent circuit transpiled to a layout suited for neutral-atom hardware, featuring CZ parallelism of 2 and a single global Hadamard layer. Ry gates with various angles and some Hadamard gates on selected qubits are applied sequentially. Green-shaded blocks indicate global single-qubit gates, and purple-shaded blocks indicate groups of parallel CZ gates. This transpilation minimizes sequential single-qubit gates while maximizing global operations.
• Figure 2: QCrank circuit with 4 address and 8 data qubits including noise channels. Only the initial barrier-separated cycles are shown; the full circuit is deeper. Final measurements are omitted. Purple (green) shaded blocks indicate global two-qubit (single qubit) gates, leveraging the DPQA's native parallelism. Yellow boxes indicated different noise channels detailed in Table \ref{['tab:noisy_gates']}, added to simulate noise expected on DPQA. The start/stop labels refer to the section of the circuit analyzed in more details in Fig. \ref{['fig:noZone-moves']}.
• Figure 3: Atoms placing and movement patterns for the circuit segment in Fig. \ref{['fig:qcrank_4+8']} (between start & stop barriers). White diamonds denote designated SLM spots where atoms can stay locked; 4 address (8 data) qubits are labeled with 'a' ('d'); entangling pulses are denoted with purple shades. See text for the details.
• Figure 4: Dependence of inaccuracy of QCrank vs. input size, for the same number of 3000 shots per address. Simulated QPU backend types: ideal (circle); neutral atoms (stars) with salmon band reflecting results obtained by changing the baseline noise level by $\pm30\%$; trapped ions (diamonds). Results from real IBM Fez QPU ar shown as crosses.
• Figure 5: Simulated residual for encoding of 128 real value sequence using QCrank 4+8. (a) Ideal simulator. Dashed diagonal line denotes perfect data recovery. (b) Noisy DPQA simulator output. Dynamic range is reduced to 67% due to noise. (c) Noisy output is scaled in post-processing to recover the full dynamic range. (d) Histogrammed residual for data from c).