Small Quantum Low Parity Density Check Codes for Near-Term Experiments

TL;DR

This work addresses the practical benchmarking of quantum error correction on near-term devices by introducing small quantum LDPC codes built from bicycle-like constructions with weight-4 stabilizers. It provides a concrete construction framework, analyzes syndrome extraction and decoding with a MWPM decoder, and demonstrates small codes with competitive performance to rotated surface codes while offering substantially lower overhead. The authors also outline two near-term experimental paths—flip-chip superconducting qubits and spin qubits with electron shuttling—to realize non-local parity checks required by these codes. The results suggest roughly a twofold overhead reduction for small distances and favorable code-rate scaling enabled by non-local connectivity, offering a tangible route toward holistic hardware benchmarks and eventual scalable quantum error correction.

Abstract

It is widely accepted that quantum error correction is essential for realizing large-scale fault-tolerant quantum computing. Recent experiments have demonstrated error correction codes operating below threshold, primarily using local planar codes such as the surface code and color code. In parallel, theoretical advances in quantum low-density parity-check (LDPC) codes promise significantly lower overheads, albeit at the cost of requiring non-local parity checks. While these results are encouraging, implementing such codes remains challenging for near-term experiments, creating obstacles to holistic benchmarking of hardware architectures capable of supporting long-range couplers. In this work, we present a simple construction recipe for small quantum LDPC codes based on recent developments in the field. Our codes are approximately twice as efficient as comparable surface codes, yet require only weight-four parity checks, which simplifies experimental realization compared to other quantum LDPC codes. We provide concrete proposals for implementations with superconducting qubits in flip-chip architectures and with semiconductor spin qubits using shuttling-based approaches.

Figures (8)

• Figure 1: (a) The visualization of the [[12,2,3]] code. Data qubits are in blue, $Z$ parity checks in green and $X$ parity checks in orange. The grey lines represent the code connectivity. The open lines symbolize periodic boundary conditions. (b) The circuit representation of the one cycle of the code.
• Figure 2: (a) If the error extraction circuit is not constructed correctly, the circuit will create an entangled state between the $Z$ and $X$ stabilizer auxiliary qubits mediated by the red gates. (b) In a good circuit, the entangling gates commute fully and disentangle the auxiliary qubits from each other through the green gates. Thus, the effictive stabilizer measurements fully commute.
• Figure 3: Logical error rate per logical qubit, $P_L$, when decoded with a minimal-weight perfect-matching decoder as a function of the physical error rate $P_p$. (a) The quantum LDPC codes constructed in the main text. (b) Rotated surface code encoding a single logical qubit.
• Figure 4: Larger codes illustrated with the data qubits in blue, the $X$-type auxillarity qubits in orange and the $Z$-type auxiliary qubits in green. (a) A $[[24,4,3]]$ code constructed with $l=4$ and $m=3$. (b) A $[[56,4,5]]$ code constructed with $l=4$ and $m=7$. (c) A $[[104,4,7]]$ code constructed with $l=4$ and $m=13$.
• Figure 5: Comparison of the code rates for our codes and the surface code. The rate $R=k/n$ is shown as a function of the code distance $d$ for the quantum LDPC codes in Fig. \ref{['fig:codes']} (blue) and for the rotated surface code (orange).