Hey AI, Generate Me a Hardware Code! Agentic AI-based Hardware Design & Verification

TL;DR

The paper addresses RTL design and verification bottlenecks in increasingly complex ICs by introducing an agentic AI-based, HITL-enabled multi-agent system (MAS) that automates end-to-end RTL and formal verification. It details a planning-development-execution methodology, a modular MAS architecture, and evaluation across five open-source designs using GPT-4o, achieving around 95% coverage and up to 100% with HITL. Key contributions include iterative RTL and SVA generation, critic-driven quality control, and a scalable, tool-agnostic framework that integrates with industry EDA tools. The work demonstrates the practical potential of autonomous AI-assisted hardware verification, while outlining directions for deeper coordination, explainability, and automated testbench generation.

Abstract

Modern Integrated Circuits (ICs) are becoming increasingly complex, and so is their development process. Hardware design verification entails a methodical and disciplined approach to the planning, development, execution, and sign-off of functionally correct hardware designs. This tedious process requires significant effort and time to ensure a bug-free tape-out. The field of Natural Language Processing has undergone a significant transformation with the advent of Large Language Models (LLMs). These powerful models, often referred to as Generative AI (GenAI), have revolutionized how machines understand and generate human language, enabling unprecedented advancements in a wide array of applications, including hardware design verification. This paper presents an agentic AI-based approach to hardware design verification, which empowers AI agents, in collaboration with Humain-in-the-Loop (HITL) intervention, to engage in a more dynamic, iterative, and self-reflective process, ultimately performing end-to-end hardware design and verification. This methodology is evaluated on five open-source designs, achieving over 95% coverage with reduced verification time while demonstrating superior performance, adaptability, and configurability.

Figures (4)

• Figure 1: Agentic design patterns
• Figure 2: Agentic AI methodology for RTL design and verification with HITL
• Figure 3: Illustration of agentic AI workflow execution
• Figure 4: Comparison of coverage results produced by proposed and zero-shot approaches