Efficient Gate Reordering for Distributed Quantum Compiling in Data Centers

TL;DR

The paper tackles distributing monolithic quantum circuits across a network of QPUs, where inter-device entanglement constitutes a key cost. It introduces a greedy gate-reordering and packing strategy, combined with a hypergraph-based partitioning, to minimize entanglement usage measured in EPR pairs. Empirical benchmarks on random circuits and QASMBench demonstrate substantial reductions in distribution cost compared to baseline approaches, validating the effectiveness of gate reordering for distributed quantum compilation. The work lays groundwork for hardware-aware extensions and multiple communication protocols to further optimize distributed quantum computing in data-center environments.

Abstract

Just as classical computing relies on distributed systems, the quantum computing era requires new kinds of infrastructure and software tools. Quantum networks will become the backbone of hybrid, quantum-augmented data centers, in which quantum algorithms are distributed over a local network of quantum processing units (QPUs) interconnected via shared entanglement. In this context, it is crucial to develop methods and software that minimize the number of inter-QPU communications. Here we describe key features of the quantum compiler araQne, which is designed to minimize distribution cost, measured by the number of entangled pairs required to distribute a monolithic quantum circuit using gate teleportation protocols. We establish the crucial role played by circuit reordering strategies, which strongly reduce the distribution cost compared to a baseline approach.

Figures (8)

• Figure 1: Distributed quantum computing as the core of quantum-augmented data centers. The upper part shows the network configuration of QPUs interconnected by entangled states (wavy lines). The entangled states are stored in communication qubits (green dots) while data qubits (white dots) are dedicated to processing. The lower part shows the workflow of the quantum compiler that implements the mapping of a monolithic algorithm to such a distributed quantum architecture. The input monolithic algorithm is optimally partitioned with respect to entanglement resources required for the interconnection, which results to its distributed version.
• Figure 2: Workflow of the araQne compiler: starting from a monolithic circuit, gates are reordered to maximize gate packet size while preserving circuit equivalence (dark and light green boxes in the circuits). The circuit is then transformed into a weighted hypergraph, which is partitioned and mapped to a distributed circuit by allocating qubits to a network of QPUs. This qubit allocation strategy helps reduce the number of required EPR pairs.
• Figure 3: Any gate packet can be expressed as in Equation \ref{['gate_packet_identity']}, and can be implemented using the circuit shown above.
• Figure 4: (Top) Example of gate packets, identified by boxes with shades of green. The gate $(3)$ highlighted in red is either diagonal or anti-diagonal so that $\mathcal{P}_1$ fulfills the definition of a gate packet. The numbers are associated with the position of gates as they appear in the figure. (Bottom) Resulting circuit after performing gate-reordering and packet-merging. The gate (7) in blue is assumed to be diagonal and in that case, gates (7) and (8) commute. The packets $\mathcal{Q}_2$ and $\mathcal{Q}_2$ have been obtained by permuting gates (8) and (7) and by merging smaller packets (see text for details). Specifically, packets $\mathcal{P}_2$ and $\mathcal{P}_4$ are merged into packet $\mathcal{Q}_2$, and packets $\mathcal{P}_3$ and $\mathcal{P}_5$ are merged into packet $\mathcal{Q}_2$.
• Figure 5: Weighted hypergraph obtained from the circuit in Fig. \ref{['comm-gates']}. The dark green hyperedge corresponds to packet $\mathcal{Q}_2$, which is the only packet acting on qubits $\{q_1, q_3, q_4\}$, and therefore has weight $1$. In contrast, the light green hyperedge has weight $2$ because two packets, namely $\mathcal{P}_1$ and $\mathcal{Q}_3$, act on qubits $\{q_1, q_2\}$.

Theorems & Definitions (12)

• Definition 1: Gate packet
• Definition 2: Allocation map
• Proposition 1: Cost of distributing a gate packet
• Definition 3: Packing sequence
• Definition 4: Distribution cost
• Proposition 2: Distribution cost after merging
• Proposition B.1: Characterization of a gate packet
• proof
• Proposition B.2: Cost of distributing a gate packet
• proof