Adiabatic Capacitive Neuron: An Energy-Efficient Functional Unit for Artificial Neural Networks

TL;DR

These results demonstrate that adiabatic charge recovery, combined with a robust low-offset threshold logic design, enables substantial energy reduction while maintaining reliable neuron operation across wide operating conditions.

Abstract

This paper introduces a new, highly energy-efficient, Adiabatic Capacitive Neuron (ACN) hardware implementation of an Artificial Neuron (AN) with improved functionality, accuracy, robustness and scalability over previous work. The paper describes the implementation of a \mbox{12-bit} single neuron, with positive and negative weight support, in an $\mathbf{0.18μm}$ CMOS technology. The paper also presents a new Threshold Logic (TL) design for a binary AN activation function that generates a low symmetrical offset across three process corners and five temperatures between $-55^o$C and $125^o$C. Post-layout simulations demonstrate a maximum rising and falling offset voltage of 9$mV$ compared to conventional TL, which has rising and falling offset voltages of 27$mV$ and 5$mV$ respectively, across temperature and process. Moreover, the proposed TL design shows a decrease in average energy of 1.5$\%$ at the SS corner and 2.3$\%$ at FF corner compared to the conventional TL design. The total synapse energy saving for the proposed ACN was above 90$\%$ (over 12x improvement) when compared to a non-adiabatic CMOS Capacitive Neuron (CCN) benchmark for a frequency ranging from 500$kHz$ to 100$MHz$. A 1000-sample Monte Carlo simulation including process variation and mismatch confirms the worst-case energy savings of $\>$90$\%$ compared to CCN in the synapse energy profile. Finally, the impact of supply voltage scaling shows consistent energy savings of above 90$\%$ (except all zero inputs) without loss of functionality.

Figures (18)

• Figure 1: N-bit Dual Tree Single Clock (DTSC) ACN design. The design consists of two sections: a capacitive synapse with SPDT switches and the threshold logic.
• Figure 2: (a) A single capacitive SPDT synapse switch showing synapse capacitor, ${C_i}$, along with bias capacitor, ${C_b}$, ballast capacitor, ${C_d}$, and the bias voltage, ${V_B}$. (b) Transistor-level diagram for a single capacitive SPDT synapse switch with synapse and ballast capacitances. (c) Power clock sinusoidal voltage wave showing the two operational modes and working phases.
• Figure 3: (a) TL design with the proposed Clocked Set-Reset latch. (b) The conventional TL with NOR-based SR latch.
• Figure 4: Transistor-level diagram of the pMOS-based DLCC (yellow shade) and proposed clocked SR latch (blue shade). (b) Layout for the proposed TL design showing the two stages and an inverter. All transistors are minimum size.
• Figure 5: The operational waveform of the two post-layout TL designs. Top trace: 1$MHz$ clock signal. Middle trace: differential inputs $v_m^+$ [red] and $v_m^-$[blue]. Bottom trace: TL outputs, proposed [green] and conventional [red]. The correct output is HIGH whenever $v_m^+>v_m^-$, so ideally, the TL should change state when red and blue traces cross. NOTE: The consistent offset in both differential directions suggests the proposed design is history-independent and performs stateless comparison.