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Mapping and Scheduling Spiking Neural Networks On Segmented Ladder Bus Architectures

Phu Khanh Huynh, Francky Catthoor, Anup Das

TL;DR

This work addresses the challenge of energy-efficient, reliable spike-traffic interconnectivity for large-scale spiking neural networks by introducing MASS, a three-stage framework for mapping, scheduling, and routing on dynamic segmented ladder bus architectures. By formulating a Hill Climbing-based cluster mapping with a composite energy-and-crossing cost, a BPPC-inspired spike scheduling heuristic, and a greedy A* routing strategy, MASS minimizes spike loss while reducing interconnect energy. Evaluations against FPGA-calibrated cycle-accurate simulations and comparisons to NoC-based and NeuSB architectures show MASS achieving substantial energy reductions and favorable EDP, with zero spike loss achievable under scheduling. The results demonstrate the practicality and impact of tailoring neuromorphic interconnects to the bursty, sparse traffic of SNNs, enabling scalable, energy-efficient hardware deployments.

Abstract

Large-scale neuromorphic architectures consist of computing tiles that communicate spikes using a shared interconnect. The communication patterns in such systems are inherently sparse, asynchronous, and localized due to the spiking nature of neural events, characterized by temporal sparsity with occasional bursts of traffic. These characteristics necessitate interconnects optimized for handling high-activity bursts while consuming minimal power during idle periods. Dynamic segmented bus has been proposed a promising interconnect for its simplicity, scalability and low power consumption. However, deploying spiking neural network applications on such buses presents challenges, including substantial inter-cluster traffic, which can lead to network congestion, spike loss, and unnecessary energy expenditure. In this paper, we propose a three-step process to deploy SNN applications on dynamic segmented buses aiming to reduce spike loss and conserve energy. Firstly, we formulate optimization heuristics to mitigate spike loss and energy consumption based on application connectivity. Secondly, we analyze the application traffic to determine spike schedules that minimize traffic flooding. Lastly, we propose a routing algorithm to minimize spike traffic path crossings. We evaluate our approach using a cycle-accurate network simulator. The simulation results show that our algorithms can eliminate spike loss while keeping energy consumption significantly lower compared to conventional NoCs.

Mapping and Scheduling Spiking Neural Networks On Segmented Ladder Bus Architectures

TL;DR

This work addresses the challenge of energy-efficient, reliable spike-traffic interconnectivity for large-scale spiking neural networks by introducing MASS, a three-stage framework for mapping, scheduling, and routing on dynamic segmented ladder bus architectures. By formulating a Hill Climbing-based cluster mapping with a composite energy-and-crossing cost, a BPPC-inspired spike scheduling heuristic, and a greedy A* routing strategy, MASS minimizes spike loss while reducing interconnect energy. Evaluations against FPGA-calibrated cycle-accurate simulations and comparisons to NoC-based and NeuSB architectures show MASS achieving substantial energy reductions and favorable EDP, with zero spike loss achievable under scheduling. The results demonstrate the practicality and impact of tailoring neuromorphic interconnects to the bursty, sparse traffic of SNNs, enabling scalable, energy-efficient hardware deployments.

Abstract

Large-scale neuromorphic architectures consist of computing tiles that communicate spikes using a shared interconnect. The communication patterns in such systems are inherently sparse, asynchronous, and localized due to the spiking nature of neural events, characterized by temporal sparsity with occasional bursts of traffic. These characteristics necessitate interconnects optimized for handling high-activity bursts while consuming minimal power during idle periods. Dynamic segmented bus has been proposed a promising interconnect for its simplicity, scalability and low power consumption. However, deploying spiking neural network applications on such buses presents challenges, including substantial inter-cluster traffic, which can lead to network congestion, spike loss, and unnecessary energy expenditure. In this paper, we propose a three-step process to deploy SNN applications on dynamic segmented buses aiming to reduce spike loss and conserve energy. Firstly, we formulate optimization heuristics to mitigate spike loss and energy consumption based on application connectivity. Secondly, we analyze the application traffic to determine spike schedules that minimize traffic flooding. Lastly, we propose a routing algorithm to minimize spike traffic path crossings. We evaluate our approach using a cycle-accurate network simulator. The simulation results show that our algorithms can eliminate spike loss while keeping energy consumption significantly lower compared to conventional NoCs.

Paper Structure

This paper contains 16 sections, 1 equation, 16 figures, 2 tables, 3 algorithms.

Figures (16)

  • Figure 1: An example of segmented ladder bus with a switch controller.
  • Figure 2: Multiple routing options in a segmented ladder bus
  • Figure 3: MASS design flow.
  • Figure 4: Example of topographically crossing.
  • Figure 5: Example of scheduling traffic.
  • ...and 11 more figures