HP2C-DT: High-Precision High-Performance Computer-enabled Digital Twin

TL;DR

HP2C-DT introduces an HPC-enabled digital twin architecture that actively integrates high-performance computing into edge-cloud workflows. By combining rolling-window data processing, phasor-based aggregation, and COMPSs-driven task orchestration, it achieves low-latency local decisions while delegating heavy computations to HPC for large-scale simulations and model updates. Experimental results in a power-grid scenario show substantial bandwidth reductions, up to 2x faster IT/OT response times, and near-ideal strong scaling up to tens of thousands of tasks across HPC resources, illustrating practical benefits for real-world complex systems. The framework provides a modular, IT/OT-integrated blueprint for deploying scalable, data-intensive digital twins across the edge-cloud-HPC continuum with strong potential for Industry 4.0 applications.

Abstract

Digital twins are transforming the way we monitor, analyze, and control physical systems, but designing architectures that balance real-time responsiveness with heavy computational demands remains a challenge. Cloud-based solutions often struggle with latency and resource constraints, while edge-based approaches lack the processing power for complex simulations and data-driven optimizations. To address this problem, we propose the High-Precision High-Performance Computer-enabled Digital Twin (HP2C-DT) reference architecture, which integrates High-Performance Computing (HPC) into the computing continuum. Unlike traditional setups that use HPC only for offline simulations, HP2C-DT makes it an active part of digital twin workflows, dynamically assigning tasks to edge, cloud, or HPC resources based on urgency and computational needs. Furthermore, to bridge the gap between theory and practice, we introduce the HP2C-DT framework, a working implementation that uses COMPSs for seamless workload distribution across diverse infrastructures. We test it in a power grid use case, showing how it reduces communication bandwidth by an order of magnitude through edge-side data aggregation, improves response times by up to 2x via dynamic offloading, and maintains near-ideal strong scaling for compute-intensive workflows across a practical range of resources. These results demonstrate how an HPC-driven approach can push digital twins beyond their current limitations, making them smarter, faster, and more capable of handling real-world complexity.

Figures (7)

• Figure 1: Reference architecture diagram.
• Figure 2: Hierarchical abstraction of digital twin objects.
• Figure 3: Power grid digital twin concept diagram.
• Figure 4: Experiment 1: Required bandwidth vs. sampling interval $T_s$ for varying numbers of edge nodes ($N=1,2,4,8$) at fixed aggregation interval $T_a=10$ s. Subfigure (a) shows the all aggregator, where bandwidth decreases with $T_s$ and scales linearly with the number of edges. Subfigure (b) shows the phasor aggregator, where bandwidth remains independent of $T_s$ but scales linearly with the number of edges.
• Figure 5: Experiment 1: Compression gain comparison for $T_a = 10$ s.