Engineering Cryogenic FETs: Addressing SCEs and Impact of Interface Traps Down to 2 K Temperature

TL;DR

This work develops and validates a TCAD-based framework to engineer cryogenic bulk-FETs from $2$ K to $300$ K, integrating 2-D electrostatics, BandTailDOS/QuantumPotential physics, and a Gaussian interface-trap model to capture SCEs. By calibrating with experimental data, it reveals that trap-induced $V_t$ shifts can create apparent $I_{ON}/I_{OFF}$ gains under fixed bias, but true performance degrades when the ON-state bias is corrected; traps also worsen $SS$ and mobility across temperatures. The spatial trap profile, quantified by $\\sigma$, governs whether SCEs are amplified (localized traps) or suppressed (broad/uniform traps), with long-channel behavior emerging beyond $L_g \\approx 150$ nm. Across oxide thicknesses, DIBL intensifies with reduced gate control and higher temperatures, while increasing temperature amplifies short-channel effects and diminishes mobility, guiding design of cryogenic CMOS nodes under real-interface conditions.

Abstract

This paper presents the design and benchmarking of cryogenic bulk-FETs using an experimentally calibrated TCAD framework that integrates 2-D electrostatics and interface-trap effects from $T = 2$ K to 300 K. For a 28-nm node device, carrier transport is predominantly ballistic at $T = 2$ K and becomes quasi-ballistic as temperature increases. At cryogenic temperatures, higher interface-trap densities increase the effective threshold voltage and suppress subthreshold conduction. However, when the ON-state bias is adjusted to account for the trap-induced $V_t$ shift, interface traps are found to \emph{worsen} $I_{\mathrm{ON}}/I_{\mathrm{OFF}}$ along with degrading the subthreshold swing (SS) and reducing mobility across all temperatures. The spatial standard deviation $σ$ of the trap distribution modulates these behaviors: highly localized traps ($σ\sim 1$--$2$ nm) exacerbate short-channel effects (SCEs), whereas broader, nearly uniform distributions ($σ\ge 50$ nm) elevate the entire barrier and suppress SCEs until saturation as $σ\to L_g$. The TCAD predictions closely match experimental data at 4.2 K, 77 K, and 300 K, providing design guidelines to optimize $I_{\mathrm{ON}}/I_{\mathrm{OFF}}$, SS, mobility, and DIBL for cryogenic CMOS technology nodes.

Figures (11)

• Figure 1: Schematic bulk MOSFET at cryogenic temperature ($T = 2 \, \text{K}$). Due to carrier freeze-out, the electron density is negligible at the mid-channel ($x = 0$). Default parameters in this work: Drain bias ($V_{\text{ds}}$) = 0 V, Oxide thickness ($T_{\text{ox}}$) = 1.5 nm, Gate length ($L_{\text{g}}$) = 28 nm, S/D doping = $6 \times 10^{20} \, \mathrm{cm^{-3}}$, S/D extension region doping = $2 \times 10^{20} \, \mathrm{cm^{-3}}$, Net S/D doping = $8 \times 10^{20} \, \mathrm{cm^{-3}}$ gate-metal work function ($\phi_m$) = 4.5 eV, substrate thickness = 1 $\mu$m, and Device width = 300 nm.
• Figure 2: TCAD deck calibration with the experimental data reported in Beckers. The ballistic model best fits across the cryogenic temperatures, with $L_{\text{ch}}$ as a ballistic prefactor defined in the TCAD module. At $T = 4.2 \, \text{K}$, nearly all carriers exhibit ballistic transport ($L_{\text{ch}} = 12 \, \text{nm}$), transitioning to quasi-ballistic transport at $T = 77 \, \text{K}$ ($L_{\text{ch}} = 42 \, \text{nm}$), and negligible ballistic transport at $T = 300 \, \text{K}$ ($L_{\text{ch}} \sim 200 \, \text{nm}$). Note that the $L_{\text{ch}}$ is not the gate length but a ballisticity parameter defined in the TCAD. Device width = 300 nm.
• Figure 3: (a) Conduction band barrier plotted at the interface for the various temperatures. (b) At zero gate bias, the carrier density increases significantly from $T = 2 \, \text{K}$ to $T = 300 \, \text{K}$, driven by the change in occupation probability and shows relatively negligible dependency on the change in surface potential. At very low temperatures ($T < 30 \, \text{K}$), the carrier density follows $n \propto \exp \left( -\frac{1}{2k_B T} \right)$. (c) & (d) For $V_{\text{gs}} > 0.4 \, \text{V}$, saturation in charge density occurs at higher temperatures, while at low temperatures, the saturation boundary is less defined.
• Figure 4: (a) Trap density-of-states $D_{\mathrm{it}}(E)$ considered in the TCAD simulations, plotted over the entire Si bandgap. The U-shaped distribution extends from the valence-band edge ($E_V = -E_g/2$) to the conduction-band edge ($E_C = +E_g/2$), with the energy axis referenced to midgap. (b) Spatial interface trap distribution is defined as a Gaussian distribution with varying standard deviation to model a highly localized trap profile ($\sigma$ = 2 nm and uniform trap distribution $\sigma \geq$ 50 nm.
• Figure 5: (a)–(c) Transfer characteristics of devices with different channel lengths ($L_{\text{g}} = 30$–$150~\text{nm}$) at $T = 2$, 77, and 300 K, using a Gaussian interface-trap distribution with $\sigma = 50~\text{nm}$ ($>\!L_{\text{g}}$). Solid and dashed curves correspond to $D_{\text{it}} = 5\times10^{11}\,\text{cm}^{-2}$ and $5\times10^{10}\,\text{cm}^{-2}$, respectively. A higher trap density raises the threshold voltage due to additional negative charge at the $\text{SiO}_2/\text{Si}$ interface. Under a fixed-bias comparison, this $V_t$ shift can produce an apparent increase in the $I_{\text{ON}}/I_{\text{OFF}}$ ratio at cryogenic temperatures. However, this effect disappears once the ON-state gate voltage is corrected for the trap-induced $V_t$ shift, and interface traps are found to degrade $I_{\text{ON}}/I_{\text{OFF}}$. Device width = 300 nm.