Frequency as a Clock: Synchronization and Intrinsic Recovery in Graphene Transistor Dynamics

TL;DR

This work addresses the origin of hysteresis and memory in graphene field-effect transistors (GFETs) under periodic gate modulation. It proposes a unified dynamic framework that treats nonequilibrium charge fluctuations $\delta n$ as governed by competing rates $g_{\mathrm{in}}(V_g)$ and $g_{\mathrm{out}}(V_g)$, yielding two regimes: intrinsic, frequency-independent relaxation with time constant $\tau$, and externally driven, frequency-locked charge transfer. For sinusoidal driving, the model predicts $\delta n(t) = \frac{\eta V_g^{\max} \tau}{\sqrt{1+(\omega \tau)^2}} \cos(\omega t + \phi)$ with $\phi = -\arctan(\omega \tau)$, linking memory window $\Delta V_{mw}$ and loop direction to drive parameters; saturation effects can be incorporated by $\eta \rightarrow \eta/\sqrt{1+\beta V_g^2}$. The work further shows that top-floating-gate devices exhibit nonvolatile, frequency-independent responses due to displacement-current–driven capacitive injection, with a bow-tie effective capacitance $C_{\mathrm{eff}}$ and gate-current signatures that corroborate the theory. Overall, the framework unifies volatile and nonvolatile graphene device dynamics, guiding interpretation of experiments and informing the design of high-frequency and neuromorphic graphene electronics.

Abstract

Hysteresis and memory effects in graphene field-effect transistors (GFETs) offer unique opportunities for neuromorphic computing, sensing, and memory applications, yet their physical origins remain debated due to competing volatile and nonvolatile interpretations. Here, we present a unified dynamic model that captures the essential physics of the GFET response under periodic gate modulation, accounting for both intrinsic relaxation processes and externally driven charge transfer. By modeling non-equilibrium carrier dynamics as a competition between injection and reabsorption rates, we uncover two distinct regimes: one governed by intrinsic, frequency-independent relaxation and another exhibiting frequency-locked behavior where the response is tied to the external drive. This distinction resolves apparent nonvolatile effects and explains loop invariance in floating-gate structures via displacement current-driven charge injection. Our framework predicts the evolution of the hysteresis loop shape, amplitude, and direction across a wide range of driving conditions, offering a versatile tool for interpreting experimental results and guiding the design of next-generation graphene-based electronic systems.

Figures (5)

• Figure 1: (a) Schematic of a graphene field-effect transistor fabricated on a SiO$_2$/Si substrate. (b) Illustration of graphene’s electronic structure modulation under gating, either via Fermi level shift or band bending. (c) Effective conductance $\sigma$ as a combination of sheet conductance $\sigma_S$ and acoustic deformation potential scattering contribution $\sigma_{ADP}$. (d) Gate voltage sweep applied to the device and their phasor representation, shown relative to the resulting carrier density fluctuation. (e) Charge fluctuation versus gate voltage loops illustrating distinct charge transfer mechanisms. Solid and dashed green lines correspond to different values of $c_g V_g$. (f) Corresponding conductance versus gate voltage loops derived from the charge modulation behavior in (e).
• Figure 2: (a) Theoretically computed charge fluctuation versus gate voltage loops as a function of pulse amplitude, in the absence of saturation effects. The green solid line indicates the ideal linear relation $c_g V_g$. (b) Corresponding conductance versus gate voltage loops derived from the carrier density profiles in (a). (c) Charge fluctuation versus gate voltage loops exhibiting saturation or exhaustion behavior due to limited charge transfer. (d) Conductance versus gate voltage loops corresponding to the saturated profiles in (c). (e,f) Results for a contrasting charge transfer mechanism, showing both carrier density (e) and the associated conductance response (f). (g) Experimentally measured conductance versus gate voltage loops under varying bottom-gate voltage amplitudes, displaying minimal sensitivity to amplitude changes. Panel (g) corresponds to a GFET without top gates.
• Figure 3: Theoretically computed charge fluctuation versus gate voltage loops as a function of pulse period. The green solid line represents the linear relation $c_g V_g$. (a) $T=2 \pi \tau/100$, (b) $T=2 \pi \tau$, and (c) $T=2 \pi \tau\cdot 100$. (d)–(f) Corresponding conductance versus gate voltage loops derived from the carrier density profiles in (a), (b), and (c), respectively. (g) Experimentally measured conductance versus gate voltage loops under varying sweep periods, demonstrating a pronounced frequency dependence of the hysteresis behavior. Panel (g) corresponds to a GFET without top gates.
• Figure 4: (a) Schematic of an encapulated hBN/graphene/hBN field-effect transistor on SiO$_2$/Si with a top floating gate electrode. (b) Diagram of the capacitive coupling between the various layers of the device structure. (c) Experimentally measured conductance versus gate voltage loops under gate voltage sweeps with varying periods: 86 s, 171 s, and 343 s. (d) Experimentally measured conductance versus gate voltage loops under different backgate sweeping from $+/-$ 10 to $+/-$ 40 V (e) Gate current measured across different periods of the applied voltage. (f) The gate capacitance extracted from the full voltage sweep. In all measuments, the top electrode is kept open, acting as a floating gate.
• Figure 5: (a) Schematic of a capacitor featuring two dielectric materials, one exhibiting polarization fluctuation. (b) Effective dynamic capacitances for forward (blue solid) and backward (red solid) voltage sweeps, alongside their constitutive stationary components (dashed curves). (c) The displacement current calculated across a range of periods for the applied gate voltage, highlighting frequency dependence. (d) The corresponding charge fluctuation versus gate voltage for different amplitudes. (e) The resultant conductance loops versus gate voltage. (f) Example of symmetric conductance loops derived from the model with fixed initialization conditions, shown for various voltage amplitudes.