SPICEMixer - Netlist-Level Circuit Evolution

TL;DR

SPICE-Mixer introduces a netlist-level genetic algorithm that evolves SPICE netlists directly, enabled by a normalization scheme that stabilizes genetic operations. By performing crossover, mutation, and pruning on normalized netlists, it effectively explores analog design spaces without bespoke encodings, and it initializes from a GraCo random sampler. Across standard cells and OpAmp synthesis, SPICE-Mixer matches or exceeds prior GraCo and CMA-ES baselines while using substantially fewer SPICE simulations, demonstrating strong practical potential for automated analog design. The work highlights normalization as a critical factor for success and outlines avenues for more aggressive pruning and domain-aware operators to further enhance performance and scalability.

Abstract

We present SPICEMixer, a genetic algorithm that synthesizes circuits by directly evolving SPICE netlists. SPICEMixer operates on individual netlist lines, making it compatible with arbitrary components and subcircuits and enabling general-purpose genetic operators: crossover, mutation, and pruning, all applied directly at the netlist level. To support these operators, we normalize each netlist by enforcing consistent net naming (inputs, outputs, supplies, and internal nets) and by sorting components and nets into a fixed order, so that similar circuit structures appear at similar line positions. This normalized netlist format improves the effectiveness of crossover, mutation, and pruning. We demonstrate SPICEMixer by synthesizing standard cells (e.g., NAND2 and latch) and by designing OpAmps that meet specified targets. Across tasks, SPICEMixer matches or exceeds recent synthesis methods while requiring substantially fewer simulations.

Figures (8)

• Figure 1: Proposed SPICE-Mixer approach. With equal probability, one of three genetic operators (pruning, mutation, or crossover) applies component or netlist mixing to generate an offspring netlist, which is then evaluated with a SPICE simulation.
• Figure 2: Example of crossover using netlist mixing for the NAND2 task. Consistent net naming (input, output, internal, supply) enables meaningful merging of parent netlists, yielding an offspring with higher reward than both parents.
• Figure 3: Example of pruning via component mixing for the NAND2 task. PMOS X4 and NMOS X5 from the parent are merged into a new NMOS, inserted as X5 after netlist normalization. The resulting offspring achieves a higher reward.
• Figure 4: SPICE simulations needed to synthesize an inverter and NAND2 for different elite set sizes $\eta$ or $\zeta$. Orange and green lines show median values for successful and all runs (including those hitting the budget of $256 \cdot 32 \cdot 3 \approx 25$k simulations). Red numbers denote failure rates (%) where we could not successfully find a circuit. In (c), we present ablation results for the NAND2 gate without applying netlist normalization; see Sec. \ref{['sec:results:subsec:ablation']} for the discussion.
• Figure 5: Number of circuits in the elite set ($\zeta = 30$, NAND2 task) generated by a specific genetic operation.