Further Characterization of the JadePix-3 CMOS Pixel Sensor for the CEPC Vertex Detector: in Dependence of Substrate Reverse Bias

TL;DR

The paper assesses JadePix-3 CMOS MAPS as a candidate for the CEPC vertex detector by systematically exploring how substrate reverse bias $V_{sub}$ influences charge collection, input capacitance, and fake-hit rate. Through a coordinated lab workflow with S-curve thresholding, ITHR scans, and seven bias points, the study demonstrates that substrate bias expands the depletion region, reduces $C_{effective}$ by over $50\%$ by $V_{sub}=-2$ V, and enhances charge collection and hit efficiency while lowering spurious hits. While reverse bias generally improves performance, excessively high bias around $-6$ V can degrade certain pixels, motivating an optimal operating point near $-5$ V. The findings establish a robust characterization framework for JadePix and guide future beam tests and R&D toward achieving the CEPC vertex detector’s stringent spatial resolution and material-budget goals.

Abstract

The Circular Electron-Positron Collider (CEPC), a proposed next-generation $e^+e^-$ collider to enable high-precision studies of the Higgs boson and potential new physics, imposes rigorous demands on detector technologies, particularly the vertex detector. JadePix-3 is a prototype Monolithic Active Pixel Sensor (MAPS) designed for the CEPC vertex detector. This paper presents a detailed laboratory-based characterization of the JadePix-3 sensor, focusing on the previously under-explored effects of substrate reverse bias voltage on key performance metrics: charge collection efficiency, average cluster size, and hit efficiency of laser. Systematic testing demonstrated that JadePix-3 operates reliably under reverse bias, exhibiting a reduced input capacitance, an expanded depletion region, enhanced charge collection efficiency, and a lower fake-hit rate. These findings confirm the sensor's potential for high-precision particle tracking and vertexing at the CEPC while offering valuable references for future iterational R\&D of the JadePix series.

Figures (21)

• Figure 1: Pixel Schematic of the JadePix-3 sensor, illustrating the main components: the collection diode, the analog front-end and the digital readout logic. The digital logic includes configuration bits for electrical pulse test (D latch1) and pixel masking (D latch2). The "Hit Register" (blue dashed box) represents the different implementations (RS latch or D flipflop) across the sensor sector designs, as detailed in Tab. \ref{['tab:digital']}. Further details on the logic operation can be found in Ref. jadepix3 (Section 2.3).
• Figure 2: Schematic diagram of the cross-section of the sensor when a reverse bias is applied to the P-substrate via a P-well.
• Figure 3: Circuit topology for the JadePix-3 analog front-end jadepix3. This analog front-end was adapted from the ALPIDE ALPIDE_upgrade sensor, featuring low power consumption of 40 nW and minimum threshold below 100 $e^-$.
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