Test and characterization of multilayer ion traps on fused silica

Abstract

Ion traps are a promising architecture to host a future quantum computer. Several challenges, such as signal-routing, power dissipation, and fabrication quality need to be overcome to scale ion trap devices to hundreds of ions. Currently, ion traps are often fabricated on silicon substrates which result in high power dissipation. Substrates that lead to lower power dissipation are preferred. In this work, we present a multi-metal layer ion trap on a fused silica substrate that is fabricated and tested in an industrial facility. Its design and material-stack are tailored to minimize power dissipation. Furthermore, we characterize the integrated temperature sensors and verify functionality down to 10 K. Moreover, we demonstrate an automated wafer test to validate each trap chip prior to its integration into experimental setups. Subsequently, we characterize electric field noise and electric stray fields using a single trapped-ion as a probe, showing an improvement in trap performance over similar trap designs realized on silicon substrates.

Figures (9)

• Figure 1: a) Optical microscope picture of the multi-metal layer ion trap used in our experiments, with different colors assigned to highlight different functional areas. The green section represents the divided bond pads for the electrical wafer test, red the RF electrodes, yellow the inner DC electrodes, and orange the outer DC electrodes. The temperature sensors (TS1 and TS2) are colored in blue, located in the first and second aluminum layer. The substrate is visible in black and the grey area is connected to GND. b) Magnification of the black marked section in a) shows three RF rails as well as DC electrodes in between. One DC electrode is marked in blue, indicating the position where ion heating rate measurements (Section \ref{['HR']}) are conducted. c) Schematic drawing of a cross-section through a connection between the first and second metal layer. The drawing shows the fused silica (FS) substrate (blue) and the ion trap's three aluminum (M1-M3) layers (green), separated by silicon oxide (SiO$_\textrm{x}$, purple).
• Figure 2: a) Illustration of the loop electrode concept: Bond pad (BP) 1a and 1b are connected through the loop line and DC1. The structural integrity of all parts is verified by measuring the connection from BP1a to BP1b (green). On the loop structures for DC2 to DC5, several types of failures that can be identified through the electrical wafer test are shown: Continuity fail (purple), DC to RF leakage (yellow), DC to DC leakage (orange), DC to GND leakage (dark red). The electrical fail of the temperature sensor is not depicted. b) Electrical wafer test results of a 200 mm wafer with 477 ion trap chips. The black lines indicate the size of a reticle shot. Every reticle shot houses 7 productive chips (squares). Different colors on the wafermap indicate pass (green) or fail (other colors, according to legend) for each trap chip during the electrical wafer test. A red star marks the chips which fail the leakage test and fit into a 3x3 grid, which corresponds to the 3x3 size of one reticle shot.
• Figure 3: a) Schematic of the temperature sensor test concept. R$_M$ represents the resistance of the meander, while R$_{C1-4}$ describes the contact resistances between needles and pads, and R$_{W1-4}$ refers to the resistance from the wires. b) and c) show the resistance curve of the two integrated temperature sensors (TS1 and TS2) over the range of 10 to 300K. The insets of Figures 3b and 3c provide a magnified view of the region between 10 K to 30 K, denoted by the red area.
• Figure 4: a) Measured heating rates as a function of axial mode frequency at different sites indicated in \ref{['fig:Trap24_overview']}a). The purple line shows a power law fit ($\dot{\bar{n}} \propto \omega^{-\alpha}$) with $\alpha = 2.0(9)$ to the heating rate data. b) Stray field measurement over a distance of 1.2mm.
• Figure 5: The lumped circuit model with resistance R, capacitance C, inductance L and conductance G.