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Constructive community race: full-density spiking neural network model drives neuromorphic computing

Johanna Senk, Anno C. Kurth, Steve Furber, Tobias Gemmeke, Bruno Golosio, Arne Heittmann, James C. Knight, Eric Müller, Tobias Noll, Thomas Nowotny, Gorka Peraza Coppola, Luca Peres, Oliver Rhodes, Andrew Rowley, Johannes Schemmel, Tim Stadtmann, Tom Tetzlaff, Gianmarco Tiddia, Sacha J. van Albada, José Villamar, Markus Diesmann

TL;DR

The PD14 model provides a canonical benchmark for neuromorphic computing by modeling full cortical microcircuitry below $1\,\text{mm}^2$ with about $10^5$ neurons and $10^9$ synapses, avoiding downscaling uncertainties. The paper compiles cross-platform performance data, defines $q_{\mathrm{RTF}}$ and $E_{\mathrm{syn}}$, and documents dramatic improvements over time—from multi-minute runtimes to real-time operation on dedicated hardware—while emphasizing accuracy validation against reference data. It discusses drivers and bottlenecks, advocates a unified benchmarking recipe and simulator-independent model reference, and highlights implications for multi-area brain modeling and energy-efficient computing. The work underscores a convergence of general-purpose and neuromorphic architectures and provides a roadmap for robust, reproducible benchmarking across future hardware and models. Finally, it calls for diversified benchmarks to capture varying computational demands and to guide scalable, energy-aware neuromorphic design.

Abstract

The local circuitry of the mammalian brain is a focus of the search for generic computational principles because it is largely conserved across species and modalities. In 2014 a model was proposed representing all neurons and synapses of the stereotypical cortical microcircuit below $1\,\text{mm}^2$ of brain surface. The model reproduces fundamental features of brain activity but its impact remained limited because of its computational demands. For theory and simulation, however, the model was a breakthrough because it removes uncertainties of downscaling, and larger models are less densely connected. This sparked a race in the neuromorphic computing community and the model became a de facto standard benchmark. Within a few years real-time performance was reached and surpassed at significantly reduced energy consumption. We review how the computational challenge was tackled by different simulation technologies and derive guidelines for the next generation of benchmarks and other domains of science.

Constructive community race: full-density spiking neural network model drives neuromorphic computing

TL;DR

The PD14 model provides a canonical benchmark for neuromorphic computing by modeling full cortical microcircuitry below with about neurons and synapses, avoiding downscaling uncertainties. The paper compiles cross-platform performance data, defines and , and documents dramatic improvements over time—from multi-minute runtimes to real-time operation on dedicated hardware—while emphasizing accuracy validation against reference data. It discusses drivers and bottlenecks, advocates a unified benchmarking recipe and simulator-independent model reference, and highlights implications for multi-area brain modeling and energy-efficient computing. The work underscores a convergence of general-purpose and neuromorphic architectures and provides a roadmap for robust, reproducible benchmarking across future hardware and models. Finally, it calls for diversified benchmarks to capture varying computational demands and to guide scalable, energy-aware neuromorphic design.

Abstract

The local circuitry of the mammalian brain is a focus of the search for generic computational principles because it is largely conserved across species and modalities. In 2014 a model was proposed representing all neurons and synapses of the stereotypical cortical microcircuit below of brain surface. The model reproduces fundamental features of brain activity but its impact remained limited because of its computational demands. For theory and simulation, however, the model was a breakthrough because it removes uncertainties of downscaling, and larger models are less densely connected. This sparked a race in the neuromorphic computing community and the model became a de facto standard benchmark. Within a few years real-time performance was reached and surpassed at significantly reduced energy consumption. We review how the computational challenge was tackled by different simulation technologies and derive guidelines for the next generation of benchmarks and other domains of science.

Paper Structure

This paper contains 37 sections, 2 equations, 3 figures, 2 tables.

Table of Contents

  1. Introduction
  2. Results
  3. Time to solution
  4. Energy to solution
  5. Discussion
  6. Methods
  7. Technology and study details
  8. NEST CPU
  9. vAl+18 VanAlbada18_291
  10. Kur+22 Kurth_2022
  11. NEST GPU
  12. Gol+21 Golosio21_627620
  13. Gol+23a Golosio23_9598
  14. GeNN
  15. KN18 Knight18_941
  16. ...and 22 more sections

Figures (3)

  • Figure 1: Spiking network model of full circuitry below $1\,\text{mm}^2$ surface area of cerebral cortex serves as benchmark for neuromorphic technologies. The statistics (dark cyan curve) of the simulated activity (dark cyan dots) is compared to reference data (thick yellow curve). Once sufficient accuracy is confirmed, the power measured during the simulation phase (light gray background) yields the consumed energy (dark cyan area corresponds to end point of light red curve, dark blue area indicates network construction phase, dark gray idle phase). The performance benchmark result (dark cyan star) contrasts the real-time factor (defined as the ratio of required wall-clock time and biological time covered by the model) against the required energy (expressed as energy per synaptic event). Network sketch (left) reproduced from VanAlbada18_291.
  • Figure 2: Progress of the community in reduction of time to solution and energy consumption for the PD14 model. Colors group hardware architectures and shapes indicate algorithmic approach (legend). Abbreviations in panels further disambiguate individual studies. a Ratio between time passed on wall-clock and stretch of time covered by the model (real-time factor) versus the year of publication in semi logarithmic representation. b Real-time factor as a function of energy per synaptic event in double logarithmic representation. Dashed line from fit through all data points with a slope of one. c Real-time factor versus process node in double logarithmic representation. Dashed line from fit through CPU and GPU data points with a slope of two. Citations of studies and values are given in Table \ref{['tab:performance']}.
  • Figure 3: Sketches of computing platforms. Diagrams illustrate the major computational building blocks and the communication architecture of a particular system required during the simulation phase. Compare with columns "# Nodes" and "System" in Table \ref{['tab:performance']}. Same color scheme as in Fig. \ref{['fig:performance']}. NEST CPU uses compute nodes with two CPU sockets each. The first study (vAl+18a/b) uses a compute cluster with Infiniband switch. The second study uses two point-to-point connected nodes (Kur+22a/b). NEST GPU and GeNN simulations run on single GPUs. SpiNNaker uses a router and 18 low-power cores per socket, with sockets embedded in a mesh routing fabric with 6 links per socket, enabling an extensible system facilitating multicast communication between cores. The presented studies using SpiNNaker both used this architecture, with variations in how the cores were configured to perform neural processing, and small variations in the overall size of the systems. CsNN uses the IBM INC-3000 system which consists of 16 PCB's (INC-cards), each hosting 27 reconfigurable SoC nodes. The whole INC-3000 system consists of 432 FPGA nodes which are connected by a 3-dimensional mesh. neuroAIx uses a cluster of 35 FPGAs connected with overlayed long hop topologies as an extension to mesh-like network topologies. BrainScaleS uses a circuit-switched on-wafer network for spike communication between the 384 ASICs per wafer.