ReChisel: Effective Automatic Chisel Code Generation by LLM with Reflection

TL;DR

This work tackles the challenge of automatic Chisel code generation by LLMs, a task where baseline performance lags behind Verilog generation. It introduces ReChisel, an LLM-based agentic system that employs a reflection loop to iteratively refine generated Chisel code using feedback from compilation and simulation, plus an escape mechanism to avoid non-progress loops. Evaluations across VerilogEval, HDLBits, and RTLLM benchmarks with five LLMs show that ReChisel substantially improves success rates, achieving performance near state-of-the-art Verilog-generation systems. The results demonstrate the viability of Chisel as a target for LLM-assisted hardware design and provide an open-source implementation for broader use.

Abstract

Coding with hardware description languages (HDLs) such as Verilog is a time-intensive and laborious task. With the rapid advancement of large language models (LLMs), there is increasing interest in applying LLMs to assist with HDL coding. Recent efforts have demonstrated the potential of LLMs in translating natural language to traditional HDL Verilog. Chisel, a next-generation HDL based on Scala, introduces higher-level abstractions, facilitating more concise, maintainable, and scalable hardware designs. However, the potential of using LLMs for Chisel code generation remains largely unexplored. This work proposes ReChisel, an LLM-based agentic system designed to enhance the effectiveness of Chisel code generation. ReChisel incorporates a reflection mechanism to iteratively refine the quality of generated code using feedback from compilation and simulation processes, and introduces an escape mechanism to break free from non-progress loops. Experiments demonstrate that ReChisel significantly improves the success rate of Chisel code generation, achieving performance comparable to state-of-the-art LLM-based agentic systems for Verilog code generation.

Figures (8)

• Figure 1: Proportion of different error types in generated Chisel code.
• Figure 2: ReChisel workflow: ReChisel is an LLM-based agentic system designed to enhance the effectiveness of Chisel code generation.
• Figure 3: Example of compiler feedback and revision plan.
• Figure 4: Example of non-progress loop. The LLM is expected to provide default values when defining the signal to ensure fully initialization. However, it repeatedly attempts to add default statements within the switch block.
• Figure 5: Illustration of escape mechanism.