Enhancing Test Efficiency through Automated ATPG-Aware Lightweight Scan Instrumentation

TL;DR

This work tackles the rising challenge of testability in complex ICs by introducing LITE, a lightweight ATPG-aware scan instrumentation that uses XOR and MUX additions to functional scan flip-flops to expose hard-to-control and hard-to-observe nets without altering normal operation. The authors present a complete automated flow (hypergraph-based netlist analysis, SCOAP-guided net selection, and configurable LITE insertions) and four configurations, plus a formal netlist generation process for seamless integration with commercial ATPG tools. Empirical evaluation on ISCAS89 and ITC99 benchmarks demonstrates that LITE achieves substantial reductions in test patterns and cycles (average ≈31.8%) while maintaining 100% fault coverage, with significantly lower area overhead than traditional test point insertion. The results show improved random-pattern testability, enabling efficient BIST and 3D/chiplet-based test strategies, and point to future work on custom scan cells, optimal SFF selection, and extension to 3D/BIST contexts.

Abstract

Scan-based Design-for-Testability (DFT) measures are prevalent in modern digital integrated circuits to achieve high test quality at low hardware cost. With the advent of 3D heterogeneous integration and chiplet-based systems, the role of scan is becoming ever more important due to its ability to make internal design nodes controllable and observable in a systematic and scalable manner. However, the effectiveness of scan-based DFT suffers from poor testability of internal nodes for complex circuits at deep logic levels. Existing solutions to address this problem primarily rely on Test Point Insertion (TPI) in the nodes with poor controllability or observability. However, TPI-based solutions, while an integral part of commercial practice, come at a high design and hardware cost. To address this issue, in this paper, we present LITE, a novel ATPG-aware lightweight scan instrumentation approach that utilizes the functional flip-flops in a scan chain to make multiple internal nodes observable and controllable in a low-cost, scalable manner. We provide both circuit-level design as well as an algorithmic approach for automating the insertion of LITE for design modifications. We show that LITE significantly improves the testability in terms of the number of patterns and test coverage for ATPG and random pattern testability, respectively, while incurring considerably lower overhead than TPI-based solutions.

Figures (8)

• Figure 1: Traditional scan operation and improved scan operation with LITE integration in a design.
• Figure 2: Elements of a scan chain: (a) A single original FF with no scan. (b) Original FF driven by MUXed logic in traditional scan architecture, and (c) The single unit of the scan FF integrated with LITE.
• Figure 3: Integrating LITE into the existing ASIC design flow and interfacing with commercial DFT tool (e.g., Synopsys TestMax) for improved testability.
• Figure 4: LITE: Configuration with observability improvement logic (no CC).
• Figure 5: LITE: Configuration with observability (Obs.) and controllability (CC) improvement logic.