QMIO: A tightly integrated hybrid HPCQC system

TL;DR

QMIO tackles the challenge of deploying production-grade, on-premises HPC–quantum hybrids by co-locating a 32-qubit QPU, a 34-qubit quantum emulator, and an HPC cluster, all under a purpose-built software stack. It advances hardware integration (cryogenics, control electronics, and high-performance networking) and software architecture (integration middleware and the QAT toolchain) to support both batch and interactive hybrid workloads. Two middleware designs—direct QCN integration and a gateway-based ZeroMQ approach—are explored, with the gateway design delivering lower latency and better user concurrency while preserving exclusive QPU access when needed. The work documents operational lessons from real deployment, including calibration/monitoring regimes and design trade-offs, and outlines a practical path toward scalable, multi-QPU HPC–QC ecosystems.

Abstract

High-Performance Computing (HPC) systems are the most powerful tools that we currently have to solve complex scientific simulations. Quantum computing (QC) has the potential to enhance HPC systems by accelerating the execution of specific kernels that can be offloaded to a Quantum Processing Unit (QPU), granting them new capabilities, improving the speed of computation, or reducing energy consumption. In this paper, we present QMIO: a state-of-the-art hybrid HPCQC system, which tightly integrates HPC and QC. We describe its hardware and software components, the integration middleware, and the lessons learned during the design, implementation, and operation of the system.

Figures (8)

• Figure 1: Overview of QMIO's hardware architecture. It is mainly composed of a HPC system, a quantum computer with a 32-qubit QPU, and classical quantum circuit emulator able to emulate up to 34 qubits. All the systems are locally interconnected and have access to a shared storage.
• Figure 2: Diagram showing the location of the various components in the data floor. On the left side, the classic HPC components are located together with the quantum emulation machines and the storage and connectivity equipment. This equipment shares space with other CESGA clusters. On the right side, there are all the components that are responsible for ensuring the functionality of the quantum hardware. Both sides are divided by a glass wall and interconnected under the raised technical floor.
• Figure 3: Schematic showing Left: Room-temperature control hardware as described in section \ref{['sec:ctrl-hw']}; Right: Cryogenic assembly as described in section \ref{['sec:cryo']}.
• Figure 4: HPCQC software stack overview. On the top of the stack are the user applications written in high level frameworks like Qiskit. The integration middleware abstracts away the details of the underlying infrastructure. On the bottom layer the quantum toolchain takes care of all the low-level operations.
• Figure 5: HPCQC integration middleware design: a) Integration of the Quantum Control Node as an HPC Compute Node. The Quantum Control Node is directly managed by the resource manager (SLURM). The Quantum Control Node runs a resource manager daemon (slurmd) as any other HPC Compute Node. The resource manager allocates this node to the jobs that request to use a QPU. b) Quantum Control Node integration using a message bus: The Gateway Node is just a standard HPC Compute Node. The allocation of the Gateway Node is managed by the resource manager (SLURM). The Gateway Node is connected with the Quantum Control Node using a message bus, in our current implementation based on ZeroMQ.