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Enable Lightweight and Precision-Scalable Posit/IEEE-754 Arithmetic in RISC-V Cores for Transprecision Computing

Qiong Li, Chao Fang, Longwei Huang, Jun Lin, Zhongfeng Wang

TL;DR

This work tackles the challenge of enabling light-weight, precision-scalable posit arithmetic within RISC-V for transprecision computing while maintaining IEEE-754 compatibility. It introduces a unified architecture that integrates dedicated posit codecs into the FPU, supports multi/mixed-precision with a dynamic exponent size $es$, and adds custom ISA extensions for format conversions between posit and IEEE-754 formats. Experimental results show substantial hardware savings (up to 47.9% LUTs and 57.4% FFs) and up to 2.54x throughput improvements in GEMM kernels, with minimal core overhead and solid SoC performance. The proposed design delivers practical transprecision capabilities on IoT-class cores, enabling efficient compute across FPU, core, and SoC levels.

Abstract

While posit format offers superior dynamic range and accuracy for transprecision computing, its adoption in RISC-V processors is hindered by the lack of a unified solution for lightweight, precision-scalable, and IEEE-754 arithmetic compatible hardware implementation. To address these challenges, we enhance RISC-V processors by 1) integrating dedicated posit codecs into the original FPU for lightweight implementation, 2) incorporating multi/mixed-precision support with dynamic exponent size for precision-scalability, and 3) reusing and customizing ISA extensions for IEEE-754 compatible posit operations. Our comprehensive evaluation spans the modified FPU, RISC-V core, and SoC levels. It demonstrates that our implementation achieves 47.9% LUTs and 57.4% FFs reduction compared to state-of-the-art posit-enabled RISC-V processors, while achieving up to 2.54$\times$ throughput improvement in various GEMM kernels.

Enable Lightweight and Precision-Scalable Posit/IEEE-754 Arithmetic in RISC-V Cores for Transprecision Computing

TL;DR

This work tackles the challenge of enabling light-weight, precision-scalable posit arithmetic within RISC-V for transprecision computing while maintaining IEEE-754 compatibility. It introduces a unified architecture that integrates dedicated posit codecs into the FPU, supports multi/mixed-precision with a dynamic exponent size , and adds custom ISA extensions for format conversions between posit and IEEE-754 formats. Experimental results show substantial hardware savings (up to 47.9% LUTs and 57.4% FFs) and up to 2.54x throughput improvements in GEMM kernels, with minimal core overhead and solid SoC performance. The proposed design delivers practical transprecision capabilities on IoT-class cores, enabling efficient compute across FPU, core, and SoC levels.

Abstract

While posit format offers superior dynamic range and accuracy for transprecision computing, its adoption in RISC-V processors is hindered by the lack of a unified solution for lightweight, precision-scalable, and IEEE-754 arithmetic compatible hardware implementation. To address these challenges, we enhance RISC-V processors by 1) integrating dedicated posit codecs into the original FPU for lightweight implementation, 2) incorporating multi/mixed-precision support with dynamic exponent size for precision-scalability, and 3) reusing and customizing ISA extensions for IEEE-754 compatible posit operations. Our comprehensive evaluation spans the modified FPU, RISC-V core, and SoC levels. It demonstrates that our implementation achieves 47.9% LUTs and 57.4% FFs reduction compared to state-of-the-art posit-enabled RISC-V processors, while achieving up to 2.54 throughput improvement in various GEMM kernels.

Paper Structure

This paper contains 12 sections, 4 figures, 4 tables.

Table of Contents

  1. Introduction
  2. Background
  3. The Proposed Architecture
  4. Lightweight Posit-Enabled RISC-V Core
  5. Efficient Precision-Scalable Posit Computing
  6. Instructions for IEEE-754 Compatible Posit Arithmetic
  7. Experimental Results
  8. FPU-level Evaluation
  9. Core-level Evaluation
  10. SoC-level Evaluation
  11. Comparison to SOTA Posit-enabled RISC-V Processors
  12. Conclusion

Figures (4)

  • Figure 1: Comparison between posit and IEEE-754 format. (a) and (b) show the respective decoding manner; (c) provides two P(16,2) decoding instances; (d) shows the decimal accuracy of the two formats under various ranges.
  • Figure 2: (a) Architecture of posit-enabled RI5CY RISC-V core, with a zoom on (b) extended FPU that supports unified posit/IEEE-754 arithmetic and (c) custom posit control and status register (pcsr).
  • Figure 3: Enhanced microarchitecture that supports dynamic exponent size and multi/mixed-precision posit/IEEE-754 arithmetic.
  • Figure 4: FPGA implemented results for modified (a) FPU and (b) RI5CY core.