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High Throughput QC-LDPC Decoder With Optimized Schedule Policy in Layered Decoding

Dongxu Chang, Qingqing Peng, Guanghui Wang, Guiying Yan

TL;DR

The paper tackles the hardware bottleneck of memory conflicts in high-throughput QC-LDPC layered decoders by optimizing the layer scheduling to minimize idle cycles while preserving decoding performance. It recasts the scheduling problem as an asymmetric TSP, introduces graph modifications to favor low-memory-conflict orders, and validates that the resulting schedules achieve both low latency and strong error-correcting performance for 5G NR LDPC codes. Key findings show that accounting for decoding performance in scheduling reduces performance degradation typically associated with idle-time optimization, enabling more efficient pipelined decoders. The approach has practical implications for implementing high-throughput LDPC decoders in contemporary standards like 5G NR.

Abstract

In this study, a scheduling policy of layered decoding for quasi-cycle (QC) low-density parity-check (LDPC) codes with high throughput and good performance is designed. The influence of scheduling on the delay of the decoder's hardware implementation and on the decoding performance are considered simultaneously. Specifically, we analyze the idle time required under various scheduling sequences within a pipelined decoding architecture and formulate the problem as a traveling salesman problem (TSP) aiming at minimizing idle time. Furthermore, considering that different scheduling sequences can affect decoding performance, we refine the graph used to solve the TSP based on scheduling characteristics that promote improved decoding outcomes. Simulation results demonstrate that the identified scheduling sequence achieves a low number of hardware delays while maintaining excellent decoding performance for 5G New Radio (NR) LDPC codes.

High Throughput QC-LDPC Decoder With Optimized Schedule Policy in Layered Decoding

TL;DR

The paper tackles the hardware bottleneck of memory conflicts in high-throughput QC-LDPC layered decoders by optimizing the layer scheduling to minimize idle cycles while preserving decoding performance. It recasts the scheduling problem as an asymmetric TSP, introduces graph modifications to favor low-memory-conflict orders, and validates that the resulting schedules achieve both low latency and strong error-correcting performance for 5G NR LDPC codes. Key findings show that accounting for decoding performance in scheduling reduces performance degradation typically associated with idle-time optimization, enabling more efficient pipelined decoders. The approach has practical implications for implementing high-throughput LDPC decoders in contemporary standards like 5G NR.

Abstract

In this study, a scheduling policy of layered decoding for quasi-cycle (QC) low-density parity-check (LDPC) codes with high throughput and good performance is designed. The influence of scheduling on the delay of the decoder's hardware implementation and on the decoding performance are considered simultaneously. Specifically, we analyze the idle time required under various scheduling sequences within a pipelined decoding architecture and formulate the problem as a traveling salesman problem (TSP) aiming at minimizing idle time. Furthermore, considering that different scheduling sequences can affect decoding performance, we refine the graph used to solve the TSP based on scheduling characteristics that promote improved decoding outcomes. Simulation results demonstrate that the identified scheduling sequence achieves a low number of hardware delays while maintaining excellent decoding performance for 5G New Radio (NR) LDPC codes.

Paper Structure

This paper contains 11 sections, 1 theorem, 5 equations, 5 figures, 1 table.

Table of Contents

  1. Introduction
  2. Preliminaries
  3. Belief Propagation for LDPC Codes
  4. Layered Belief Propagation and Scheduling Sequences
  5. Idle Cycles in Pipelining
  6. Scheduling with Small Idle Time And Good Performance
  7. The TSP for Solving Memory Conflicts
  8. Optimization of Idle Time And Decoding Performance
  9. Simulation Results
  10. Conclusion
  11. Proof of Proposition \ref{['prop1']}

Key Result

Proposition 1

Let the variable nodes be uniformly randomly connected to the check nodes, and denote the minimum degree of the layers by $d_{min}$. Assume that $t\leq d_{min}$ and $N$ approaches infinity. Then prioritizing the update of low-degree check nodes before high-degree check nodes can yield the minimum ex

Figures (5)

  • Figure 1: Idle cycle in the pipelined decoding architecture.
  • Figure 2: The graph $\mathcal{G}$ for TSP with 4 layers.
  • Figure 3: The modified graph $\mathcal{G}$ for TSP with 4 layers. The dashed edges represent weights of positive infinity.
  • Figure 4: Error-correcting performance for various scheduling policies under different code rates and information lengths. The 5G NR LDPC codes constructed from BG1 are evaluated. The latency of the SO data path $t$ is 4.
  • Figure 5: Error-correcting performance for various scheduling policies under different code rates and information lengths. The 5G NR LDPC codes constructed from BG1 are evaluated. The latency of the SO data path $t$ is 9.

Theorems & Definitions (3)

  • Definition 1: scheduling sequences
  • Proposition 1
  • proof