Transient Slack Capability

TL;DR

This paper defines Transient Slack Capability (TSC) as three device-level conditions—storage capacity, a controlled input power, and control-driven energy balance—within a port-Hamiltonian framework to ensure stability under sustained power perturbations. It establishes how the time-scale interaction between storage, control, and perturbations governs TSC and validates the concept numerically on a WSCC 9-bus system with both Grid-Following and Grid-Forming converters. The work shows that TSC can be achieved with appropriate slack control and internal energy-balance mechanisms, while also highlighting the role of current limiters and inertia-less (VSM) strategies in shaping stability. The PH-based, technology-agnostic approach provides a unified lens for assessing and designing device-level stability across diverse inverter controls, with implications for future slack models and control schemes.

Abstract

This paper introduces the concept of Transient Slack Capability (TSC), a set of three necessary device-level conditions to ensure stability under sustained power perturbations. TSC states that a device must (1) possess sufficient stored energy; (2) a controlled input power; and (3) maintain internal energy balance and synchronization. The paper shows that the relation among the time-scales of storage, control, and power perturbation is at the core of the TSC concept. Using the port-Hamiltonian (PH) framework, these conditions are formalized and validated via simulations on an adapted model of the WSCC 9-bus system. Case studies demonstrate that TSC is achievable in both Grid-Following (GFL) and Grid-Forming (GFM) converter control schemes, provided the conditions above are satisfied. Sensitivity analysis serves to identify storage and power reserve requirements to meet Conditions 1 and 2; the impact of converter current limiters on Condition 3; and inertia-less solutions able to achieve TSC.

Figures (6)

• Figure 1: Cases 1, 2 and 3 --- Positive load step at bus 5 --- (a) pll Frequency $\omega$ for gfl at bus 1, (b) ac voltage magnitude at bus 1 $v_{\mathrm{ac}}$, (c) dc voltage for gfl 1 $v_{\mathrm{dc}}$ and (d) Active power deliver at bus 1 $p_{\mathrm{1}}$.
• Figure 2: Case 3 --- Positive load step at bus 5 --- (a) Real and imaginary parts of critical eigenvalues for different values of $C_{\mathrm{dc}}$ for ibr at buses 1, 2, and 3; (b) Real parts of critical eigenvalues as a function of $C_{\mathrm{dc}}$ for ibr at buses 1, 2, and 3; (c) dc voltage $v_{\mathrm{dc}}$ for gfl 1 for different values of $C_{\mathrm{dc}}$; (d) dc input current $\imath^{\star}_{\mathrm{dc}}$ for gfl 1 for different values of $C_{\mathrm{dc}}$.
• Figure 3: Case 3 --- Positive load step at bus 5 --- (a) Real and imaginary part of critical eigenvalues for different values of $T_{\mathrm{slack}}$ for ibr at buses 1, 2 and 3, (b) Real part of critical eigenvalues as a function of $C_{\mathrm{dc}}$ for ibr at buses 1, 2 and 3, (c) dc voltage for gfl 1 $v_{\mathrm{dc}}$ for different values of $T_{\mathrm{slack}}$ and (d) dc input current for gfl 1 $\imath^{\star}_{\mathrm{dc}}$ for different values of $T_{\mathrm{slack}}$.
• Figure 4: Case 4 and 5 --- Positive load step at bus 5 --- (a) dc voltage and (b) dc input current for ibr 1.
• Figure 5: Case 5 --- Positive load step at bus 5 --- (a) Frequency of ibr 1, 2 and 3 for unlimited current output (b) Frequency of ibr 1, 2 and 3 for limited current gfm Droop schemes.