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Simulation-Guided Approximate Logic Synthesis Under the Maximum Error Constraint

Chang Meng, Weikang Qian, Giovanni De Micheli

TL;DR

This work tackles ALS under a stringent maximum error constraint by introducing a simulation-guided flow that prunes and selects LACs using logic simulation and SAT solving. The key innovations are a CPM-based lower-bound computation for MaxError to prune invalid LACs and a greedy, simulation-guided LAC selection strategy that efficiently applies multiple LACs per iteration. Empirical results show dramatic runtime improvements (up to 30.6x faster than prior state-of-the-art) and meaningful reductions in area and delay, with scalability to large EPFL benchmarks. The method also demonstrates robustness across MaxED and MaxHD metrics and outperforms typical approaches on approximate adders and multipliers, indicating strong practical impact for energy-efficient, error-tolerant designs.

Abstract

Approximate computing is an effective computing paradigm for improving the energy efficiency of error-tolerant applications. Approximate logic synthesis (ALS) is an automatic process to generate approximate circuits with reduced area, delay, and power, while satisfying user-specified error constraints. This paper focuses on ALS under the maximum error constraint. As an essential error metric that provides a worst-case error guarantee, the maximum error is crucial for many applications such as image processing and machine learning. This work proposes an efficient simulation-guided ALS flow that handles this constraint. It utilizes logic simulation to 1) prune local approximate changes (LACs) with large errors that violate the error constraint, and 2) accelerate the SAT-based LAC selection process. Furthermore, to enhance scalability, our ALS flow iteratively selects a set of promising LACs satisfying the error constraint to improve efficiency. The experimental results show that compared with the state-of-the-art method, our ALS flow accelerates by 30.6x, and further reduces the circuit area and delay by 18.2% and 4.9%, respectively. Notably, our flow scales to large EPFL benchmarks with up to 38540 nodes, which remain challenging for existing ALS methods tackling maximum error constraint.

Simulation-Guided Approximate Logic Synthesis Under the Maximum Error Constraint

TL;DR

This work tackles ALS under a stringent maximum error constraint by introducing a simulation-guided flow that prunes and selects LACs using logic simulation and SAT solving. The key innovations are a CPM-based lower-bound computation for MaxError to prune invalid LACs and a greedy, simulation-guided LAC selection strategy that efficiently applies multiple LACs per iteration. Empirical results show dramatic runtime improvements (up to 30.6x faster than prior state-of-the-art) and meaningful reductions in area and delay, with scalability to large EPFL benchmarks. The method also demonstrates robustness across MaxED and MaxHD metrics and outperforms typical approaches on approximate adders and multipliers, indicating strong practical impact for energy-efficient, error-tolerant designs.

Abstract

Approximate computing is an effective computing paradigm for improving the energy efficiency of error-tolerant applications. Approximate logic synthesis (ALS) is an automatic process to generate approximate circuits with reduced area, delay, and power, while satisfying user-specified error constraints. This paper focuses on ALS under the maximum error constraint. As an essential error metric that provides a worst-case error guarantee, the maximum error is crucial for many applications such as image processing and machine learning. This work proposes an efficient simulation-guided ALS flow that handles this constraint. It utilizes logic simulation to 1) prune local approximate changes (LACs) with large errors that violate the error constraint, and 2) accelerate the SAT-based LAC selection process. Furthermore, to enhance scalability, our ALS flow iteratively selects a set of promising LACs satisfying the error constraint to improve efficiency. The experimental results show that compared with the state-of-the-art method, our ALS flow accelerates by 30.6x, and further reduces the circuit area and delay by 18.2% and 4.9%, respectively. Notably, our flow scales to large EPFL benchmarks with up to 38540 nodes, which remain challenging for existing ALS methods tackling maximum error constraint.

Paper Structure

This paper contains 30 sections, 8 equations, 6 figures, 7 tables.

Table of Contents

  1. Introduction
  2. Related Works
  3. Approximate Logic Synthesis (ALS) Methods
  4. Error Estimation Methods for ALS
  5. Background
  6. Logic Circuit Terminologies
  7. Maximum Error Metrics
  8. Error Miter for Maximum Error Checking
  9. Methodology
  10. Overview
  11. Simulation-Guided LAC Pruning
  12. Theoretical Foundation
  13. Efficient Computation of the Maximum Error Lower Bounds
  14. Promising LAC Selection and Application Based on Simulation-Guided SAT Solving
  15. Formulation of the LAC Selection Problem
  16. ...and 15 more sections

Figures (6)

  • Figure 1: An error miter that checks whether the maximum error of the approximate circuit $\hat{G}$ exceeds the error bound $B$ or not.
  • Figure 2: Simulation-guided ALS flow under the maximum error constraint.
  • Figure 3: An example circuit. The number above each wire is the signal value under the $i$-th input pattern in the simulation. The impact of the LAC that replaces node $n$ with node $x_2$ is considered.
  • Figure 4: Greedy promising LAC selection strategy supported by simulation-guided SAT solving.
  • Figure 5: Impact of simulation count on final area after applying our method and runtime of our method under $\lfloor 2^{O/5}\rfloor$ MaxED constraint. Runtime data differs from that in Table \ref{['tab:res_maxed']} since a different computer is used in this experiment.
  • ...and 1 more figures

Theorems & Definitions (2)

  • Example 1
  • Example 2