Abstractions-of-Thought: Intermediate Representations for LLM Reasoning in Hardware Design

TL;DR

Abstractions-of-Thought (AoT) tackles the challenge of generating functionally correct HDL from natural language by introducing a training-free prompting framework that decomposes problems into high-level classification, problem-specific IR, and line-by-line pseudocode, enabling better mapping to Verilog RTL. The approach leverages hardware design abstractions and a multi-model prompting strategy to improve functional accuracy, especially with large LLMs like GPT-4o, while reducing token overhead relative to Tree-of-Thought. Empirical evaluation on the VerilogEval benchmark shows AoT improves functionality for large models and can outperform baseline prompting strategies; a multi-model setup further boosts results for smaller models by assigning abstraction generation to a larger model. Ablation studies reveal that both IR and pseudocode contribute to improvements, with full AoT providing the strongest gains and a clear indication that structured abstractions can generalize to other engineering tasks. The work emphasizes practical implications for faster hardware prototyping with LLMs and outlines avenues to extend the framework to more complex designs and other engineering domains.

Abstract

Large language models (LLMs) have achieved impressive proficiency on logic and programming tasks, often rivaling expert-level performance. However, generating functionally correct hardware description language (HDL) code from natural language specifications remains challenging, primarily in data-scarce domains. Therefore, we present Abstractions-of-Thought (AoT) - a training-free, inference-only prompting framework to mitigate misinterpretations and reasoning pitfalls of LLMs through a series of task-based abstractions within the prompting procedure, assisting in the transition from high-level to low-level representations of hardware. Furthermore, AoT consists of the following stages: (1) an LLM-based classification of hardware design patterns, (2) a structured intermediate representation (IR) to separate functional decomposition from code syntax, and (3) a line-by-line pseudocode solution enabling a more direct mapping to the final Verilog implementation. Experimental results on the VerilogEval benchmark depict that AoT demonstrates improvements in functionality when applied to large non-reasoning models (such as GPT-4o, outperforming all baseline techniques (including 1-shot, Chain-of-Thought, and Tree-of-Thought) while significantly reducing the generated tokens by 1.8-5.2x compared to popular Tree-of-Thought prompting.

Figures (4)

• Figure 1: AoT Framework — abstractions for generating hardware designs.
• Figure 2: Classification prompt ($C_2$).
• Figure 3: Counter module IR abstraction.
• Figure 4: Counter module pseudocode abstraction.