Hardware-Level QoS Enforcement Features: Technologies, Use Cases, and Research Challenges

TL;DR

Hardware-level QoS enforcement features on commodity x86 processors enable per-class resource control to mitigate shared-resource interference in cloud environments. The authors conduct a comprehensive snowball-based survey of 78 papers (from an initial 3685) and propose a taxonomy that separates feature evaluations, black-box controllers, and application-aware strategies. Key findings include that most evaluations focus on Intel CAT/MBA with AMD QoSE underrepresented, that QoS is inherently indirect, and that adoption in general-purpose clouds remains limited. The paper highlights opportunities to integrate QoS control with hypervisors and container schedulers, extend to multi-machine/data-center settings, and develop platform-agnostic abstractions.

Abstract

Recent advancements in commodity server processors have enabled dynamic hardware-based quality-of-service (QoS) enforcement. These features have gathered increasing interest in research communities due to their versatility and wide range of applications. Thus, there exists a need to understand how scholars leverage hardware QoS enforcement in research, understand strengths and shortcomings, and identify gaps in current state-of-the-art research. This paper observes relevant publications, presents a novel taxonomy, discusses the approaches used, and identifies trends. Furthermore, an opportunity is recognized for QoS enforcement utilization in service-based cloud computing environments, and open challenges are presented.

Figures (13)

• Figure 1: Illustration of a typical three-level cache architecture.
• Figure 2: Illustration of a cache partitioning scheme for a CPU supporting $8$ bits of control ($0_{16}$ to $\textrm{FF}_{16}$). Here, COS0 has exclusive access to $2/8 = 1/4$ of available cache, while COS1 and COS2 share parts of their allocation.
• Figure 3: Illustration of the shared memory bus of a modern Intel Xeon Scalable processor mulnix_intel_2022.
• Figure 4: Illustration of memory bandwidth limiting (MBL) impact on the memory request chain. Bandwidth limiting affects all requests that miss the L2 cache, which includes potential L3 hits.
• Figure 5: Reference snowballing search strategy used.