WISP: Image Segmentation-Based Whitespace Diagnosis for Optimal Rectilinear Floorplanning

TL;DR

WISP targets whitespace diagnosis in rectilinear floorplanning, where traditional $HPWL$ is ill-suited for irregular boundaries. It introduces an image segmentation-based floorplan parsing workflow to identify wasted whitespace, followed by a Gaussian Mixture Model ($GMM$) whitespace density scoring and a direction-aware simulated annealing refinement for macro placement. The approach yields consistent improvements in routing wirelength ($rWL$) and timing metrics ($WNS$, $TNS$) and enables block-level area recycling back to the top-level floorplan, averaging $16.2\%$ area reduction. Across nine benchmarks, WISP achieves an average $rWL$ improvement of $5.4\%$ (max $11.4\%$) and average reductions of $WNS$ and $TNS$ by $41.5\%$ and $43.7\%$, respectively, demonstrating practical impact for rectilinear floorplanning.

Abstract

The increasing number of rectilinear floorplans in modern chip designs presents significant challenges for traditional macro placers due to the additional complexity introduced by blocked corners. Particularly, the widely adopted wirelength model Half-Perimeter Wirelength (HPWL) struggles to accurately handle rectilinear boundaries, highlighting the need for additional objectives tailored to rectilinear floorplan optimization. In this paper, we identify the necessity for whitespace diagnosis in rectilinear floorplanning, an aspect often overlooked in past research. We introduce WISP, a novel framework that analyzes and scores whitespace regions to guide placement optimization. WISP leverages image segmentation techniques for whitespace parsing, a lightweight probabilistic model to score whitespace regions based on macro distribution, a Gaussian Mixture Model (GMM) for whitespace density scoring and direction-aware macro relocation to iteratively refine macro placement, reduce wasted whitespace, and enhance design quality. The proposed diagnostic technique also enables the reclamation of block-level unused area and its return to the top level, maximizing overall area utilization. When compared against state-of-the-art academia placer DREAMPlace 4.1, our method achieves an average improvement of 5.4% in routing wirelength, with a maximum of 11.4% across widely-used benchmarks. This yields an average of 41.5% and 43.7% improvement in Worst Negative Slack (WNS) and Total Negative Slack (TNS), respectively. Additionally, WISP recycles an average of 16.2% area at the block level, contributing to more efficient top-level area distribution.

Figures (11)

• Figure 1: (a) Illustration of the hierarchical floorplanning methodology, showcasing an optimization process from the top-level floorplan to the block-level rectilinear module floorplan. At the top level, modules are transformed from regular rectangles into rectilinear shapes to improve area utilization. The block-level floorplanning starts with a suboptimal placement, where inefficient usage of space leads to noticeable wasted whitespace. The optimized result highlights how effective whitespace analysis and reuse can significantly improve floorplan quality and area efficiency. (b) Challenges in current rectilinear floorplanning, including increased possibilities in wasted whitespace, the creation of notch-induced dead zones, and the limitations of traditional wirelength models such as HPWL in capturing the true layout characteristics of rectilinear modules.
• Figure 2: (a) Original top-level floorplan with whitespace as discussed in jigsawplanner. (b) Top-level floorplan with modules converted into rectilinear blocks.
• Figure 3: (a) Wasted whitespace regions can lead to long routing. (b) Impact of wasted whitespace in rectilinear floorplanning.
• Figure 4: Comparison between traditional algorithms and our proposed Image Segmentation-inspired method for whitespace analysis.
• Figure 5: The overall flow of the proposed WISP methodology.