RISC-Q: A Generator for Real-Time Quantum Control System-on-Chips Compatible with RISC-V

TL;DR

RISC-Q tackles the challenge of scalable quantum control by delivering an open source QCSoC generator with a RISC-V interface, enabling automated, parameterized hardware software co design for diverse quantum platforms. Built with SpinalHDL, it abstracts peripherals, supports MMIO and custom instructions, and leverages a TileLink interconnect to streamline integration. A superconducting qubit case study on RFSoC demonstrates parity with state of the art like QICK and QubiC while substantially reducing HDL code and facilitating on chip measurement and calibration workflows. By providing an interoperable, extensible platform, RISC-Q accelerates hardware software co design and paves the way for practical, scalable quantum control systems.

Abstract

Quantum computing imposes stringent requirements for the precise control of large-scale qubit systems, including, for example, microsecond-latency feedback and nanosecond-precision timing of gigahertz signals -- demands that far exceed the capabilities of conventional real-time systems. The rapidly evolving and highly diverse nature of quantum control necessitates the development of specialized hardware accelerators. While a few custom real-time systems have been developed to meet the tight timing constraints of specific quantum platforms, they face major challenges in scaling and adapting to increasingly complex control demands -- largely due to fragmented toolchains and limited support for design automation. To address these limitations, we present RISC-Q -- an open-source flexible generator for Quantum Control System-on-Chip (QCSoC) designs, featuring a programming interface compatible with the RISC-V ecosystem. Developed using SpinalHDL, RISC-Q enables efficient automation of highly parameterized and modular QCSoC architectures, supporting agile and iterative development to meet the evolving demands of quantum control. We demonstrate that RISC-Q can replicate the performance of existing QCSoCs with significantly reduced development effort, facilitating efficient exploration of the hardware-software co-design space for rapid prototyping and customization.

Figures (5)

• Figure 1: A Schematic Overview of the RISC-Q hardware architecture for Quantum Control System-on-Chip (QCSoC). The RFSP program refers to programs that process Radio-Frequency Signal Processing tasks.
• Figure 2: Software and hardware stack of RISC-Q. Blue boxes indicate components implemented within the RISC-Q framework.
• Figure 3: An example dataflow of superconducting qubit measurement in RISC-Q. RefTime is a 32-bit reference clock increased by 1 in every cycle for precise phase and timing.
• Figure 4: Integration of memories and peripherals in RISC-Q. Red boxes indicate memories connected via the TileLink bus. Orange boxes represent peripherals integrated through MMIO and custom instructions.
• Figure 5: Custom instruction for RF signal generation. id specifies the RF signal generator to be used.