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Frequency-Dependent Power Consumption Modeling of CMOS Transmitters for WNoC Architectures

Mohammad Shahmoradi, Korkut Kaan Tokgöz, Eduard Alarcón, Sergi Abadal

TL;DR

This work addresses the challenge of energy‑efficient WNoC CMOS transmitters by building frequency‑dependent behavioral descriptions of the three most power‑hungry TX sub‑blocks: PA, oscillator, and mixer. Using prototype surveys up to THz frequencies, it derives a TX‑level DC power framework where $P_{ ext{DC,PA}}(f)$ follows an exponential trend with frequency, oscillators stay under ~10 mW up to ~200 GHz, and mixers exhibit modest, frequency‑dependent DC power with CG tied to $P_{ ext{DC}}$. Integrating these into a full RF front‑end model for WNoC reveals clear regimes: at low frequencies and low PA drive, oscillator power dominates; as frequency or PA drive increases, the PA becomes the main power sink. The approach enables rapid exploration of operating points to identify optimal $f$ for energy efficiency and can be extended to receiver modeling for a complete transceiver optimization in on‑chip wireless links.

Abstract

Wireless Network-on-Chip (WNoC) systems, which wirelessly interconnect the chips of a computing system, have been proposed as a complement to existing chip-to-chip wired links. However, their feasibility depends on the availability of custom-designed high-speed, tiny, ultra-efficient transceivers. This represents a challenge due to the tradeoffs between bandwidth, area, and energy efficiency that are found as frequency increases, which suggests that there is an optimal frequency region. To aid in the search for such an optimal design point, this paper presents a behavioral model that quantifies the expected power consumption of oscillators, mixers, and power amplifiers as a function of frequency. The model is built on extensive surveys of the respective sub-blocks, all based on experimental data. By putting together the models of the three sub-blocks, a comprehensive power model is obtained, which will aid in selecting the optimal operating frequency for WNoC systems.

Frequency-Dependent Power Consumption Modeling of CMOS Transmitters for WNoC Architectures

TL;DR

This work addresses the challenge of energy‑efficient WNoC CMOS transmitters by building frequency‑dependent behavioral descriptions of the three most power‑hungry TX sub‑blocks: PA, oscillator, and mixer. Using prototype surveys up to THz frequencies, it derives a TX‑level DC power framework where follows an exponential trend with frequency, oscillators stay under ~10 mW up to ~200 GHz, and mixers exhibit modest, frequency‑dependent DC power with CG tied to . Integrating these into a full RF front‑end model for WNoC reveals clear regimes: at low frequencies and low PA drive, oscillator power dominates; as frequency or PA drive increases, the PA becomes the main power sink. The approach enables rapid exploration of operating points to identify optimal for energy efficiency and can be extended to receiver modeling for a complete transceiver optimization in on‑chip wireless links.

Abstract

Wireless Network-on-Chip (WNoC) systems, which wirelessly interconnect the chips of a computing system, have been proposed as a complement to existing chip-to-chip wired links. However, their feasibility depends on the availability of custom-designed high-speed, tiny, ultra-efficient transceivers. This represents a challenge due to the tradeoffs between bandwidth, area, and energy efficiency that are found as frequency increases, which suggests that there is an optimal frequency region. To aid in the search for such an optimal design point, this paper presents a behavioral model that quantifies the expected power consumption of oscillators, mixers, and power amplifiers as a function of frequency. The model is built on extensive surveys of the respective sub-blocks, all based on experimental data. By putting together the models of the three sub-blocks, a comprehensive power model is obtained, which will aid in selecting the optimal operating frequency for WNoC systems.
Paper Structure (11 sections, 3 equations, 5 figures)

This paper contains 11 sections, 3 equations, 5 figures.

Table of Contents

  1. Introduction
  2. Methodology
  3. Modeling of Power consumption in Power Amplifiers
  4. Modeling of Power consumption in Oscillators
  5. Modeling of Power consumption in Mixers
  6. Results
  7. Behavioral Power Model of the Power Amplifier
  8. Behavioral Power Model of the Fundamental Oscillator
  9. Behavioral Power Model of the Mixer
  10. RF Front-End Behavioral Power Model for WNoC
  11. Conclusion

Figures (5)

  • Figure 1: Wireless Network-on-Chip (WNoC) architecture in a multi-chip system. The inset shows a simplified RF front-end for the TX.
  • Figure 2: Frequency-dependent PAE model based on best-in-class data from wang2020power(top) and resulting $\mathrm{P_{DC, PA}}$ for multiple $\mathrm{P_{in}}$ configurations (bottom).
  • Figure 3: Frequency-dependent oscillator model: DC-to-RF efficiency (top) and $\mathrm{P_{DC, Osc}}$ for varying $\mathrm{P_{RF,~out}}$ (bottom).
  • Figure 4: Mixer power consumption model as a function of frequency (top) and derived model for $\mathrm{P_{DC,~Mixer}}$ (bottom).
  • Figure 5: TX front-end DC power contribution for different mixer $\mathrm{P_{out}}$ levels, with $\mathrm{P_{IF}} = -5$ dBm. Top: $\mathrm{P_{out,PA}}$ and $\mathrm{P_{out,Osc}}$ = 0 dBm. Bottom: $\mathrm{P_{out,PA}}$ = 5 dBm, $\mathrm{P_{out,Osc}}$ = 0 dBm.