Physics-Aware Compilation for Parallel Quantum Circuit Execution on Neutral Atom Arrays

TL;DR

This work tackles the difficulty of efficiently compiling circuits for scalable neutral-atom quantum computers, which offer hardware flexibility through reconfigurable trap geometries. It introduces Physics-Aware Compilation (PAC), a framework that leverages hardware physics via Hardware Plane Partitioning and Quantum Circuit Division to decompose a global mapping problem into manageable local optimizations. The approach uses an improved Kernighan-Lin algorithm with a physics-informed loss to minimize cross-region gates and maximize local parallelism, yielding substantial speedups with minimal loss in circuit quality. Experimental results show PAC achieving up to $202.81\times$ speedups on 24×24 and $139.16\times$ on 64×64 arrays, while keeping circuit depth comparable to state-of-the-art methods, demonstrating strong scalability for large neutral-atom arrays. Overall, PAC provides a practical path toward deploying large-scale neutral-atom quantum computers by aligning compilation techniques with the underlying physical hardware.

Abstract

Neutral atom quantum computers are one of the most promising quantum architectures, offering advantages in scalability, dynamic reconfigurability, and potential for large-scale implementations. These characteristics create unique compilation challenges, especially regarding compilation efficiency while adapting to hardware flexibility. However, existing methods encounter significant performance bottlenecks at scale, hindering practical applications. We propose Physics-Aware Compilation (PAC), a method that improves compilation efficiency while preserving the inherent flexibility of neutral atom systems. PAC introduces physics-aware hardware plane partitioning that strategically allocates hardware resources based on physical device characteristics like AOD and SLM trap properties and qubit mobility constraints. Additionally, it implements parallel quantum circuit division with an improved Kernighan-Lin algorithm that enables simultaneous execution across independent regions while maintaining circuit fidelity. Our experimental evaluation compares PAC with state-of-the-art methods across increasingly larger array sizes ranging from 16x16 to 64x64 qubits. Results demonstrate that PAC achieves up to 78.5x speedup on 16x16 arrays while maintaining comparable circuit quality. PAC's compilation efficiency advantage increases with system scale, demonstrating scalability for practical quantum applications on larger arrays. PAC explores a viable path for practical applications of neutral atom quantum computers by effectively addressing the tension between compilation efficiency and hardware flexibility.

Figures (11)

• Figure 1: A reconfigurable atom array with AOD and SLM traps.
• Figure 2: Illustration of AOD crossing constraint violation.
• Figure 3: Qubit transition from AOD to SLM trap for entanglement formation.
• Figure 4: Workflow of PAC.
• Figure 5: Demonstration of hardware plane partitioning.