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2T1R Regulated Memristor Conductance Control Array Architecture for Neuromorphic Computing using 28nm CMOS Technology

Neethu Kuriakose, Arun Ashok, Christian Grewing, André Zambanini, Stefan van Waasen

TL;DR

This paper tackles the challenge of scalable, low-power in-memory computation with memristor crossbars for vector-matrix multiplication, where sneak-path currents and supply drops hinder performance. It presents a regulated 2T1R memristor conductance-control architecture with dual-mode (voltage and current) programming, local regulation, and grounded non-selected terminals to suppress sneak paths, paired with a current-mode SAR ADC for readout. The authors demonstrate a 2×2 crossbar in 28 nm CMOS with a dedicated MEMCTRL block and a RISC-V controller, achieving regulated conductance control while reducing readout power and avoiding virtual-ground issues. The work offers a practical path toward neuromorphic CIM implementations by enabling precise, analog conductance programming and scalable CMOS integration.

Abstract

Memristors are promising devices for scalable and low power, in-memory computing to improve the energy efficiency of a rising computational demand. The crossbar array architecture with memristors is used for vector matrix multiplication (VMM) and acts as kernels in neuromorphic computing. The analog conductance control in a memristor is achieved by applying voltage or current through it. A basic 1T1R array is suitable to avoid sneak path issues but suffer from wire resistances, which affects the read and write procedures. A conductance control scheme with a regulated voltage source will improve the architecture and reduce the possible potential divider effects. A change in conductance is also possible with the provision of a regulated current source and measuring the voltage across the memristors. A regulated 2T1R memristor conductance control architecture is proposed in this work, which avoids the potential divider effect and virtual ground scenario in a regular crossbar scheme, as well as conductance control by passing a regulated current through memristors. The sneak path current is not allowed to pass by the provision of ground potential to both terminals of memristors.

2T1R Regulated Memristor Conductance Control Array Architecture for Neuromorphic Computing using 28nm CMOS Technology

TL;DR

This paper tackles the challenge of scalable, low-power in-memory computation with memristor crossbars for vector-matrix multiplication, where sneak-path currents and supply drops hinder performance. It presents a regulated 2T1R memristor conductance-control architecture with dual-mode (voltage and current) programming, local regulation, and grounded non-selected terminals to suppress sneak paths, paired with a current-mode SAR ADC for readout. The authors demonstrate a 2×2 crossbar in 28 nm CMOS with a dedicated MEMCTRL block and a RISC-V controller, achieving regulated conductance control while reducing readout power and avoiding virtual-ground issues. The work offers a practical path toward neuromorphic CIM implementations by enabling precise, analog conductance programming and scalable CMOS integration.

Abstract

Memristors are promising devices for scalable and low power, in-memory computing to improve the energy efficiency of a rising computational demand. The crossbar array architecture with memristors is used for vector matrix multiplication (VMM) and acts as kernels in neuromorphic computing. The analog conductance control in a memristor is achieved by applying voltage or current through it. A basic 1T1R array is suitable to avoid sneak path issues but suffer from wire resistances, which affects the read and write procedures. A conductance control scheme with a regulated voltage source will improve the architecture and reduce the possible potential divider effects. A change in conductance is also possible with the provision of a regulated current source and measuring the voltage across the memristors. A regulated 2T1R memristor conductance control architecture is proposed in this work, which avoids the potential divider effect and virtual ground scenario in a regular crossbar scheme, as well as conductance control by passing a regulated current through memristors. The sneak path current is not allowed to pass by the provision of ground potential to both terminals of memristors.
Paper Structure (12 sections, 10 equations, 10 figures, 3 tables)

This paper contains 12 sections, 10 equations, 10 figures, 3 tables.

Table of Contents

  1. Introduction
  2. ReRAM Device Model
  3. Memristor Conductance Control Modes
  4. Overview
  5. Voltage Mode Operation
  6. Current Mode Operation
  7. Read Operation
  8. Analog Conductance
  9. 2T1R Crossbar Array Architecture
  10. CMOS Implementation
  11. Conclusion
  12. Acknowledgement

Figures (10)

  • Figure 1: 1T1R including line resistances and concept of virtual ground
  • Figure 2: Equivalent circuit diagram for the electrical model (a) of the Pt/HfO2/TiOx/Pt device b4. The voltage is applied to the bottom electrode. The V-I characteristics correspond to the voltage sweep applied to the model (b)
  • Figure 3: 2T1R regulated architecture for 2x1 structure
  • Figure 4: Simplified view of regulator circuit for read-write operations
  • Figure 5: Transient analysis using read verify algorithm with layout parasitics
  • ...and 5 more figures