Writing a Good Security Paper for ISSCC (2025)

TL;DR

This paper provides a structured set of guidelines for crafting high-quality hardware security papers for ISSCC, grounded in the authors' experience on the Security Subcommittee since 2024. It articulates core evaluation criteria (innovation and significance), rigorous benchmarking practices, and category-specific requirements for cryptographic accelerators, RNG, PUF, and side-channel defenses, while advocating broader topic diversity beyond the traditional security triad. It emphasizes formal security reasoning, process-node considerations, collaboration between silicon designers and security researchers, and clear reporting of measurements, threat models, and attack coverage. The overall goal is to improve submission quality, foster diverse and impactful security research, and accelerate the field's growth within the ISSCC community.

Abstract

Security is increasingly more important in designing chips and systems based on them, and the International Solid-State Circuits Conference (ISSCC), the leading conference for presenting advances in solid-state circuits and semiconductor technology, is committed to hardware security by establishing the security subcommittee since 2024. In the past two years, the authors of this paper reviewed submissions as members of the Security Subcommittee, a part of International Technical Program Committee (ITPC). This paper aims to encourage high-quality submissions to grow this field in the overall scope of the ISSCC.