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AES-RV: Hardware-Efficient RISC-V Accelerator with Low-Latency AES Instruction Extension for IoT Security

Van Tinh Nguyen, Phuc Hung Pham, Vu Trung Duong Le, Hoai Luan Pham, Tuan Hai Vu, Thi Diem Tran

TL;DR

The paper tackles the need for fast, energy-efficient AES acceleration on resource-constrained IoT devices. It introduces AES-RV, a hardware-efficient RISC-V accelerator that combines a Specialized AES Unit with low-latency custom instructions, high-bandwidth internal buffers, and a ping-pong memory pipeline to achieve real-time multi-mode AES processing. Implemented on the Xilinx ZCU102 FPGA, AES-RV supports all AES modes and key sizes and demonstrates up to approximately 256x speedup and about 453x energy efficiency improvements over baseline CPUs, with strong area efficiency. This approach enables secure, high-performance embedded systems and lays groundwork for future extensions to post-quantum cryptography.

Abstract

The Advanced Encryption Standard (AES) is a widely adopted cryptographic algorithm essential for securing embedded systems and IoT platforms. However, existing AES hardware accelerators often face limitations in performance, energy efficiency, and flexibility. This paper presents AES-RV, a hardware-efficient RISC-V accelerator featuring low-latency AES instruction extensions optimized for real-time processing across all AES modes and key sizes. AES-RV integrates three key innovations: high-bandwidth internal buffers for continuous data processing, a specialized AES unit with custom low-latency instructions, and a pipelined system supported by a ping-pong memory transfer mechanism. Implemented on the Xilinx ZCU102 SoC FPGA, AES-RV achieves up to 255.97 times speedup and up to 453.04 times higher energy efficiency compared to baseline and conventional CPU/GPU platforms. It also demonstrates superior throughput and area efficiency against state-of-the-art AES accelerators, making it a strong candidate for secure and high-performance embedded systems.

AES-RV: Hardware-Efficient RISC-V Accelerator with Low-Latency AES Instruction Extension for IoT Security

TL;DR

The paper tackles the need for fast, energy-efficient AES acceleration on resource-constrained IoT devices. It introduces AES-RV, a hardware-efficient RISC-V accelerator that combines a Specialized AES Unit with low-latency custom instructions, high-bandwidth internal buffers, and a ping-pong memory pipeline to achieve real-time multi-mode AES processing. Implemented on the Xilinx ZCU102 FPGA, AES-RV supports all AES modes and key sizes and demonstrates up to approximately 256x speedup and about 453x energy efficiency improvements over baseline CPUs, with strong area efficiency. This approach enables secure, high-performance embedded systems and lays groundwork for future extensions to post-quantum cryptography.

Abstract

The Advanced Encryption Standard (AES) is a widely adopted cryptographic algorithm essential for securing embedded systems and IoT platforms. However, existing AES hardware accelerators often face limitations in performance, energy efficiency, and flexibility. This paper presents AES-RV, a hardware-efficient RISC-V accelerator featuring low-latency AES instruction extensions optimized for real-time processing across all AES modes and key sizes. AES-RV integrates three key innovations: high-bandwidth internal buffers for continuous data processing, a specialized AES unit with custom low-latency instructions, and a pipelined system supported by a ping-pong memory transfer mechanism. Implemented on the Xilinx ZCU102 SoC FPGA, AES-RV achieves up to 255.97 times speedup and up to 453.04 times higher energy efficiency compared to baseline and conventional CPU/GPU platforms. It also demonstrates superior throughput and area efficiency against state-of-the-art AES accelerators, making it a strong candidate for secure and high-performance embedded systems.
Paper Structure (12 sections, 1 equation, 8 figures, 1 table)

This paper contains 12 sections, 1 equation, 8 figures, 1 table.

Table of Contents

  1. Introduction
  2. Proposed AES-RV Architecture
  3. System Architecture Overview
  4. High-Bandwidth Internal Buffers for Fast Continuous Data Accessing
  5. Specialized AES Unit (SAU) with Low-Latency Custom Instruction Extension
  6. System Pipelining with a Ping-Pong Memory Transfer Mechanism
  7. Evaluation Results
  8. Implementation results on ZCU102 FPGA SoC
  9. Performance Comparison of AES-RV and Baseline RISC-V Implementation
  10. Performance and Energy Efficiency Evaluation on Real-Time Software Platforms
  11. Comprehensive Performance and Hardware Efficiency Evaluation for AES Implementations
  12. Conclusion

Figures (8)

  • Figure 1: (a) System architecture overview of AES-RV at the SoC. (b) AES-RV architecture.
  • Figure 2: High-bandwidth Buffer Set for Fast Continuous Data Accessing
  • Figure 3: Structure of the Buffer Accessing Instructions.
  • Figure 4: Specialized AES Unit and Multi-mode AES Core architecture.
  • Figure 5: Custom instruction for calling Specialized AES Unit.
  • ...and 3 more figures