Multi-Objective Memory Bandwidth Regulation and Cache Partitioning for Multicore Real-Time Systems

TL;DR

This work tackles memory bandwidth regulation and cache partitioning for multicore real-time systems under partitioned EDF scheduling. It introduces a 0-1 ILP for optimal task-resource co-allocation and a novel Multi-Objective Multi-Layer Optimization (MMO) heuristic that combines Pareto-pruned outer search with a dynamic-programming inner knapsack for efficient task allocation. Real-world validation on an embedded AMD UltraScale+ ZCU102 platform with Jailhouse-based cache coloring and MemGuard demonstrates that the 0-1 ILP outperforms previous MIP formulations, while MMO consistently achieves higher schedulability and better resource efficiency than state-of-the-art CaM, providing multiple non-dominated solutions. The results indicate practical gains in predictability and utilization for real-time MPSoCs, with implications for energy efficiency and system design flexibility. Future work includes extending the framework to parallel real-time tasks with data dependencies and broader hardware platforms.

Abstract

Memory bandwidth regulation and cache partitioning are widely used techniques for achieving predictable timing in real-time computing systems. Combined with partitioned scheduling, these methods require careful co-allocation of tasks and resources to cores, as task execution times strongly depend on available allocated resources. To address this challenge, this paper presents a 0-1 linear program for task-resource co-allocation, along with a multi-objective heuristic designed to minimize resource usage while guaranteeing schedulability under a preemptive EDF scheduling policy. Our heuristic employs a multi-layer framework, where an outer layer explores resource allocations using Pareto-pruned search, and an inner layer optimizes task allocation by solving a knapsack problem using dynamic programming. To evaluate the performance of the proposed optimization algorithm, we profile real-world benchmarks on an embedded AMD UltraScale+ ZCU102 platform, with fine-grained resource partitioning enabled by the Jailhouse hypervisor, leveraging cache set partitioning and MemGuard for memory bandwidth regulation. Experiments based on the benchmarking results show that the proposed 0-1 linear program outperforms existing mixed-integer programs by finding more optimal solutions within the same time limit. Moreover, the proposed multi-objective multi-layer heuristic performs consistently better than the state-of-the-art multi-resource-task co-allocation algorithm in terms of schedulability, resource usage, number of non-dominated solutions, and computational efficiency.

Figures (6)

• Figure 1: Slowdown profile (relative to unrestricted execution) of the mser-qcif benchmark with variable memory bandwidth $b$ and cache partition $k$ allocations. The upper inset presents the slowdown as a heatmap where both dimensions vary; the bottom insets present the resource sensitivity of each dimension separately.
• Figure 2: Slowdown profiles for representative benchmarks from different test suites. Columns present the results for one benchmark for different inputs (rows). Numerical slowdown values for the extreme configurations are indicated in the corners of each plot.
• Figure 3: Schedulability ratio (i.e., $\frac{\text{\#schedulable task sets}}{\text{\#total task sets}} \times 100$ %).
• Figure 4: Memory bandwidth usage (number of partitions).
• Figure 5: Cache usage (number of partitions).