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Lightweight LIF-only SNN accelerator using differential time encoding

Daniel Windhager, Lothar Ratschbacher, Bernhard A. Moser, Michael Lunglmayr

TL;DR

This work presents a lightweight, LIF-only SNN accelerator that leverages differential time encoding to efficiently represent and merge spike trains, enabling fast feedforward inference. A hardware spike-merger mechanism and a learned encoding strategy are introduced, with detailed synthesis results on an FPGA (Xilinx Ultrascale+) and an ASIC path using the ASAP7 PDK. The approach achieves MNIST accuracy around 99% with millisecond-scale inference times and emphasizes memory-dominated power/area due to SRAM blocks. Overall, the combination of differential-time spikes, hardware-friendly merging, and an encoding-learning loop offers a practical, energy-efficient route for edge SNN inference, with open-source tooling supporting replication and further development.

Abstract

Spiking Neural Networks (SNNs) offer a promising solution to the problem of increasing computational and energy requirements for modern Machine Learning (ML) applications. Due to their unique data representation choice of using spikes and spike trains, they mostly rely on additions and thresholding operations to achieve results approaching state-of-the-art (SOTA) Artificial Neural Networks (ANNs). This advantage is hindered by the fact that their temporal characteristic does not map well to already existing accelerator hardware like GPUs. Therefore, this work will introduce a hardware accelerator architecture capable of computing feedforward LIF-only SNNs, as well as an accompanying encoding method to efficiently encode already existing data into spike trains. Together, this leads to a design capable of >99% accuracy on the MNIST dataset, with ~0.29ms inference times on a Xilinx Ultrascale+ FPGA, as well as ~0.17ms on a custom ASIC using the open-source predictive 7nm ASAP7 PDK. Furthermore, this work will showcase the advantages of the previously presented differential time encoding for spikes, as well as provide proof that merging spikes from different synapses given in differential time encoding can be done efficiently in hardware.

Lightweight LIF-only SNN accelerator using differential time encoding

TL;DR

This work presents a lightweight, LIF-only SNN accelerator that leverages differential time encoding to efficiently represent and merge spike trains, enabling fast feedforward inference. A hardware spike-merger mechanism and a learned encoding strategy are introduced, with detailed synthesis results on an FPGA (Xilinx Ultrascale+) and an ASIC path using the ASAP7 PDK. The approach achieves MNIST accuracy around 99% with millisecond-scale inference times and emphasizes memory-dominated power/area due to SRAM blocks. Overall, the combination of differential-time spikes, hardware-friendly merging, and an encoding-learning loop offers a practical, energy-efficient route for edge SNN inference, with open-source tooling supporting replication and further development.

Abstract

Spiking Neural Networks (SNNs) offer a promising solution to the problem of increasing computational and energy requirements for modern Machine Learning (ML) applications. Due to their unique data representation choice of using spikes and spike trains, they mostly rely on additions and thresholding operations to achieve results approaching state-of-the-art (SOTA) Artificial Neural Networks (ANNs). This advantage is hindered by the fact that their temporal characteristic does not map well to already existing accelerator hardware like GPUs. Therefore, this work will introduce a hardware accelerator architecture capable of computing feedforward LIF-only SNNs, as well as an accompanying encoding method to efficiently encode already existing data into spike trains. Together, this leads to a design capable of >99% accuracy on the MNIST dataset, with ~0.29ms inference times on a Xilinx Ultrascale+ FPGA, as well as ~0.17ms on a custom ASIC using the open-source predictive 7nm ASAP7 PDK. Furthermore, this work will showcase the advantages of the previously presented differential time encoding for spikes, as well as provide proof that merging spikes from different synapses given in differential time encoding can be done efficiently in hardware.
Paper Structure (11 sections, 1 theorem, 6 equations, 7 figures, 3 tables)

This paper contains 11 sections, 1 theorem, 6 equations, 7 figures, 3 tables.

Table of Contents

  1. Introduction
  2. Background and related work
  3. Efficient spike representation
  4. Sampled time compared to differential time
  5. Comparing spike trains in differential time
  6. Hardware architecture
  7. Merging the spikes in hardware
  8. Processing the neuron layer
  9. Synthesis Results
  10. Learning the Encoding
  11. Conclusion

Key Result

Proposition 1

The ordered set $\Delta Y$ can be generated directly from $\Delta A$ and $\Delta B$ using the following procedure: Compare the first elements of the input sets $\Delta A$ and $\Delta B$ to each other. Append the minimum to the output set $\Delta Y$, remove the minimum from its respective set, and up

Figures (7)

  • Figure 1: Histogram for the difference times when using the test set of the MNIST dataset with 9x9 learned encoding as shown in Section \ref{['sec:learned_encoding']}.
  • Figure 2: Overall number of bits $B_S$ required to encode the entire spike train based on chosen bit width $b$ for the differential time.
  • Figure 3: Merging of spike sequences given in differential time.
  • Figure 4: Spike merger element capable of merging two separate spike trains given in differential time.
  • Figure 5: Hardware architecture capable of accelerating arbitrarily deep and wide feedforward networks of lif neurons iscas2024.
  • ...and 2 more figures

Theorems & Definitions (2)

  • Proposition 1
  • proof