GLOVA: Global and Local Variation-Aware Analog Circuit Design with Risk-Sensitive Reinforcement Learning

TL;DR

GLOVA targets robust analog/mixed-signal design under process, voltage, and temperature variations by formulating sizing as a constrained optimization across multiple PVT corners and mismatch scenarios. It combines risk-sensitive reinforcement learning with an ensemble-based critic to learn sizing policies that maximize reliability under uncertainty, formalized with a $J = \mathbb{E}[R] + \beta \sigma[R]$ objective. To curb verification cost, it introduces mu-sigma evaluation and a simulation reordering strategy, and supports industrial-style verification modes including corner and Monte Carlo simulations. Empirical results on real 28 nm circuits (e.g., SAL, FIA, OCSA, SH) show substantial gains in sample efficiency and runtime reduction, with notable improvements in challenging DRAM-core configurations. Collectively, GLOVA offers a scalable, practical pipeline for variation-aware analog design automation with rigorous verification support.

Abstract

Analog/mixed-signal circuit design encounters significant challenges due to performance degradation from process, voltage, and temperature (PVT) variations. To achieve commercial-grade reliability, iterative manual design revisions and extensive statistical simulations are required. While several studies have aimed to automate variation aware analog design to reduce time-to-market, the substantial mismatches in real-world wafers have not been thoroughly addressed. In this paper, we present GLOVA, an analog circuit sizing framework that effectively manages the impact of diverse random mismatches to improve robustness against PVT variations. In the proposed approach, risk-sensitive reinforcement learning is leveraged to account for the reliability bound affected by PVT variations, and ensemble-based critic is introduced to achieve sample-efficient learning. For design verification, we also propose $μ$-$σ$ evaluation and simulation reordering method to reduce simulation costs of identifying failed designs. GLOVA supports verification through industrial-level PVT variation evaluation methods, including corner simulation as well as global and local Monte Carlo (MC) simulations. Compared to previous state-of-the-art variation-aware analog sizing frameworks, GLOVA achieves up to 80.5$\times$ improvement in sample efficiency and 76.0$\times$ reduction in time.

Figures (4)

• Figure 1: Schematic of global (die-to-die) and local (within-die) variations on a wafer process_variation2. The median difference between two dies is determined by global variation ($\sigma^{\text{Global}}$), while variations within each die occur around its median due to local variation ($\sigma^{\text{Local}}$).
• Figure 2: Framework overview of the proposed GLOVA.
• Figure 3: Design reliability bound estimation under PVT variations using an ensemble-based critic trained on sampled worst-case scenarios.
• Figure 4: Schematics of three analog/mixed-signal testcase circuits.