Concept of a System-on-Chip Research Platform Benchmarking Interaction of Memristor-based Bio-inspired Computing Paradigms

TL;DR

The paper addresses the von Neumann bottleneck in AI by proposing a System-on-Chip architecture that integrates memristor-based bio-inspired computing arrays with inter- and intra-chip communication to form a scalable benchmark platform. It details a heterogeneous SoC featuring seven memristor-based computing arrays, a 32-bit Network-on-Chip, a RISC-V host with AXI access, and a chip bridge for at-speed NoC monitoring, all built atop a 28nm CMOS process with post-processing memristor integration. The work specifies concrete design constraints across fabrication, packaging, power delivery, interfaces, and testability, and outlines a plan for demonstrator development with first measurements anticipated in 2025. By enabling cross-paradigm interaction and providing quantitative benchmarks for performance, energy, and footprint, the approach aims to accelerate the evaluation of memristor-based bio-inspired paradigms against traditional CMOS baselines in a scalable, real-system context.

Abstract

A system architecture is suggested for a System on Chip that will combine several different memristor-based, bio-inspired computation arrays with inter- and intra-chip communication. It will serve as a benchmark system for future developments. The architecture takes the special requirements into account which are caused by the memristor co-integration on commercial CMOS structures in a post processing step of the chip. The interface considers the necessary data bandwidth to monitor the internal Network on Chip at speed and provides enough flexibility to give different measurement options.

Figures (1)

• Figure 1: Architecture and floorplan of the proposed SoC.