AutoRAC: Automated Processing-in-Memory Accelerator Design for Recommender Systems

TL;DR

AutoRAC tackles the data-movement bottleneck in deep-learning based recommender systems by co-designing both the DNN backbone and a Processing-In-Memory (PIM) accelerator. It casts the problem as a mixed-precision neural-architecture search over a one-shot supernet that spans a vast design space (exceeding $10^{54}$ architectures) and uses evolutionary search to identify hardware-friendly configurations, including novel mappings for dot-product and factorization-machine operators on ReRAM crossbars. The approach yields substantial gains: up to $3.4\times$ speedup, $1.7\times$ area reduction, and $12.5\times$ power efficiency over naive mappings and handcrafted baselines across three CTR benchmarks. These results demonstrate the practicality of automated, hardware-aware NAS for PIM-based recommender systems with strong potential for real-world deployment and energy-efficient inference.

Abstract

The performance bottleneck of deep-learning-based recommender systems resides in their backbone Deep Neural Networks. By integrating Processing-In-Memory~(PIM) architectures, researchers can reduce data movement and enhance energy efficiency, paving the way for next-generation recommender models. Nevertheless, achieving performance and efficiency gains is challenging due to the complexity of the PIM design space and the intricate mapping of operators. In this paper, we demonstrate that automated PIM design is feasible even within the most demanding recommender model design space, spanning over $10^{54}$ possible architectures. We propose \methodname, which formulates the co-optimization of recommender models and PIM design as a combinatorial search over mixed-precision interaction operations, and parameterizes the search with a one-shot supernet encompassing all mixed-precision options. We comprehensively evaluate our approach on three Click-Through Rate benchmarks, showcasing the superiority of our automated design methodology over manual approaches. Our results indicate up to a 3.36$\times$ speedup, 1.68$\times$ area reduction, and 12.48$\times$ higher power efficiency compared to naively mapped searched designs and state-of-the-art handcrafted designs.

Figures (6)

• Figure 1: Overview of AutoRAC framework with search space and evaluation criteria.
• Figure 2: Test Log Loss on Criteo versus weight bit-width.
• Figure 3: (a) ReRAM crossbar for FC, EFC, and DP. (b) Transposed-write ReRAM crossbar for FM.
• Figure 4: Overview of AutoRAC mapping schemes and architecture design.
• Figure 5: Percentage drop of criterion (Lower is better).