Pixel column issue in the ATLAS Inner Tracker modules

TL;DR

This work characterizes the core-column issue observed in ITkPix-based pixel modules for the ATLAS ITk inner tracker upgrade. Through production-data analysis, diced-chip probing, analog/digital scans, and mechanical-damage experiments, the study identifies mechanical damage during hybridisation and ancillary analog dependencies as key contributors to erratic CC behavior, rather than an intrinsic design flaw. The issue affects roughly one-fifth to one-quarter of ITkPix v1.1 and v2 modules, substantially impacting module yield and QA criteria. The findings motivate strengthened hybridisation QC and module-level checks for core-column faults, with ongoing simulations to assess the impact on tracking performance under realistic operation.

Abstract

Pixel modules are currently being built for the ATLAS ITk Pixel detector upgrade. During the preproduction phase, recurring chip malfunctioning was observed during electrical testing. It was possible to bypass this issue by disabling some pixel core columns in the ITkPix readout chip. Therefore the issue is called "core column issue" which is a direct disqualifier for a pixel module. A concerning number of cases has been observed in pixel modules with ITkPix v1.1 as well as v2 chips which significantly impacts the module yield. However, the behaviour is erratic and there is not any evidence hinting at the origin of this issue. These proceedings outline the investigations of the issue, highlighting the electrical behaviour during testing, present findings from the data collected via our production database and through visual inspection, and point towards possible causes of the issue.

Figures (11)

• Figure 1: Two pixel module flavours: (a) a quad module, (b) a linear triplet module.
• Figure 2: (a) The ITkPix chip layout: pixel matrix (left) with cc logic (right). (b) Occupancy map from a digital scan with 100 injections on a module with some cc disabled (marked in green). The bottom right chip was not wirebonded.
• Figure 3: Fraction of chips (a) and modules (b) with disabled core columns per hybridisation vendor. (c) positions of disabled cc on all problematic chips.
• Figure 4: (a) Cumulative wafer map with occurence of cc chip position. (b) example wafer map where cc chips often appear in consecutive oder in a row or column. The z-scale indicate the location of disabled core columns on that chip.
• Figure 5: (a) Map from a pixel test highlighting a bad 4$\times$1 pixel region. (b) Occupancy map from an analog scan with a bad 8$\times$8 pixel core with mostly 0 hits. (c) Occupancy map of a module at 1650 e injection charge. (d) Occupancy map of the same module at 2600 e injection charge.