Scalable 28nm IC implementation of coupled oscillator network featuring tunable topology and complexity

TL;DR

The paper addresses the need for scalable, hardware-implementable studies of coupled oscillator networks with tunable topology and complexity. It introduces a 28nm CMOS, PLL-based clustered architecture that embodies delayed Kuramoto dynamics through on-chip phase-to-frequency coupling, implemented via two programmable schemes CS-1 and CS-2 and a programmable delay $\tau$, with an embedded RISC-V processor for algorithmic experimentation. Key contributions include the design of an overdamped PLL with $\phi_m = 74^\circ$, a loop bandwidth of $\omega_{BW} = 2\pi \times 27\times 10^3$ rad/s, and a center frequency near 10 MHz, along with a scalable 7x7 cluster architecture and on-chip programmability. The hardware enables practical, real-time studies of synchronization and critical dynamics for analog computing and transport-network stability, demonstrated by a July 2024 tapeout and future power-grid applications.

Abstract

Integrated circuit implementations of coupled oscillator networks have recently gained increased attention. The focus is usually on using these networks for analogue computing, for example for solving computational optimization tasks. For use within analog computing, these networks are run close to critical dynamics. On the other hand, such networks are also used as an analogy of transport networks such as electrical power grids to answer the question of how exactly such critical dynamic states can be avoided. However, simulating large network of coupled oscillators is computationally intensive, with specifc regards to electronic ones. We have developed an integrated circuit using integrated Phase-Locked Loop (PLL) with modifications, that allows to flexibly vary the topology as well as a complexity parameter of the network during operation. The proposed architecture, inspired by the brain, employs a clustered architecture, with each cluster containing 7 PLLs featuring programmable coupling mechanisms. Additionally, the inclusion of a RISC-V processor enables future algorithmic implementations. Thus, we provide a practical alternative for large-scale network simulations both in the field of analog computing and transport network stability research.

Figures (7)

• Figure 1: Block diagram of the PLL, where PD is the phase detector with a gain of $K_{PD}$, CP is the charge pump with gain $I_{CP}$, LPF is the loop filter and VCO with a gain $K_{VCO}$ is voltage controlled oscillator.
• Figure 2: Step response of type-2 3rd order PLL
• Figure 3: Optimal capacitance for a certain Phase margin $\phi_{m}$
• Figure 4: Cluster architecture of coupled oscillator with 7 clusters, and 7 PLLs in each cluster. Two coupling schemes CS-1 and CS-2 as well as a programmable delay
• Figure 5: (a) Coupling scheme 1 or CS-1 (b) Coupling scheme 2 or CS-2