Self Clocked Digital LDO for Cryogenic Power Management in 22nm FDSOI with 98 Percent Efficiency

TL;DR

The paper tackles scaling quantum computers by placing cryogenic control electronics near the qubits to reduce interconnect complexity and thermal load. It develops a self-clocked DLDO in 22 nm FDSOI with backgate biasing to offset cryogenic threshold drift around $200~\\mathrm{mV}$ and uses dual-loop coarse/fine PMOS banks controlled by a peak detector. A Simulink-based small-signal model yields a discrete-time transfer function $TF(z) = \\frac{G_C \\cdot G_{out}}{(z-1)\\left(z - e^{-\\omega_{out}/f_{clk}}\\right)}$, enabling stability-aware design. Simulation results show $V_{out} = 1.7~\\mathrm{V}$ with a settle time of $1.15~\\mu s$ at $I_{load}=10~\\mathrm{mA}$ and a steady-state ripple of $4.8~\\mathrm{mV}$, with peak efficiency around the mid-90s percent range depending on load. Overall, the approach provides a practical, mismatch-tolerant, energy-efficient cryogenic regulator suitable for scalable quantum architectures.

Abstract

A universal quantum computer~(QC), though promising ground breaking solutions to complex problems, still faces several challenges with respect to scalability. Current state-of-the-art QC use a great quantity of cables to connect the physical qubits, situated in the cryogenic temperature, to room temperature electronics. Integrated cryogenic electronics together with semiconductor spin qubits is one way closer for scalability. Such a scalable quantum computer can have qubits and the control electronics at 4K stage. Being at 4K, more thermal dissipation is allowed without overloading the cooling capability of the fridge. Still, control and power circuitry is expected to be highly efficient. While commercial CMOS technologies are found to be operatable at \qty{}{mK}, lack of reliable cryogenic models while designing, increased mismatches at cryo temperatures makes the design challenging and risky. Using an FDSOI technology with backgate biasing to compensate for the threshold voltage drift happening at cryo~(compensating around 200mV) and digital circuitry is a way to address this challenge. In this work, a self-clocked digital low dropout regulator (DLDO) is designed in FDSOI for high power efficient, variation tolerant regulator to supply cryogenic circuits for Quantum computing. The proposed digital LDO is more resilient to mismatch and having self clocking and close and fine loops addresses the power efficiency and faster transient response.

Figures (8)

• Figure 1: Basic Digital LDO from b1
• Figure 2: Proposed digital LDO with coarse and fine loops driven by overshoot/undershoot detector
• Figure 3: DLDO small-signal discrete-time model b2
• Figure 4: Pole-zero plot of DLDO system.
• Figure 5: Transient response of SC-DLDO simulink model