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An Integrated UVM-TLM Co-Simulation Framework for RISC-V Functional Verification and Performance Evaluation

Ruizhi Qiu, Yang Liu

TL;DR

The paper presents an integrated UVM-TLM co-simulation framework for RISC-V processors, addressing the gap between functional verification and early performance evaluation. It introduces a configurable vmodel with credit-based pipeline flow control that co-simulates in lockstep with a Spike-based golden reference, enabling both ISA-level verification and performance trend analysis within a single environment. Experimental results show ISA conformance, high microarchitectural coverage, and substantial simulation speedups over RTL, facilitating faster design iterations and broader exploration of architectural options. The work demonstrates significant practical impact by enabling rapid validation and comparative study of microarchitectural choices early in the development cycle.

Abstract

The burgeoning RISC-V ecosystem necessitates efficient verification methodologies for complex processors. Traditional approaches often struggle to concurrently evaluate functional correctness and performance, or balance simulation speed with modeling accuracy. This paper introduces an integrated co-simulation framework leveraging Universal Verification Methodology (UVM) and Transaction-Level Modeling (TLM) for RISC-V processor validation. We present a configurable UVM-TLM model (vmodel) of a superscalar, out-of-order RISC-V core, featuring key microarchitectural modeling techniques such as credit-based pipeline flow control. This environment facilitates unified functional verification via co-simulation against the Spike ISA simulator and enables early-stage performance assessment using benchmarks like CoreMark, orchestrated within UVM. The methodology prioritizes integration, simulation efficiency, and acceptable fidelity for architectural exploration over cycle-level precision. Experimental results validate functional correctness and significant simulation speedup over RTL approaches, accelerating design iterations and enhancing verification coverage.

An Integrated UVM-TLM Co-Simulation Framework for RISC-V Functional Verification and Performance Evaluation

TL;DR

The paper presents an integrated UVM-TLM co-simulation framework for RISC-V processors, addressing the gap between functional verification and early performance evaluation. It introduces a configurable vmodel with credit-based pipeline flow control that co-simulates in lockstep with a Spike-based golden reference, enabling both ISA-level verification and performance trend analysis within a single environment. Experimental results show ISA conformance, high microarchitectural coverage, and substantial simulation speedups over RTL, facilitating faster design iterations and broader exploration of architectural options. The work demonstrates significant practical impact by enabling rapid validation and comparative study of microarchitectural choices early in the development cycle.

Abstract

The burgeoning RISC-V ecosystem necessitates efficient verification methodologies for complex processors. Traditional approaches often struggle to concurrently evaluate functional correctness and performance, or balance simulation speed with modeling accuracy. This paper introduces an integrated co-simulation framework leveraging Universal Verification Methodology (UVM) and Transaction-Level Modeling (TLM) for RISC-V processor validation. We present a configurable UVM-TLM model (vmodel) of a superscalar, out-of-order RISC-V core, featuring key microarchitectural modeling techniques such as credit-based pipeline flow control. This environment facilitates unified functional verification via co-simulation against the Spike ISA simulator and enables early-stage performance assessment using benchmarks like CoreMark, orchestrated within UVM. The methodology prioritizes integration, simulation efficiency, and acceptable fidelity for architectural exploration over cycle-level precision. Experimental results validate functional correctness and significant simulation speedup over RTL approaches, accelerating design iterations and enhancing verification coverage.
Paper Structure (14 sections, 2 figures, 2 tables)

This paper contains 14 sections, 2 figures, 2 tables.

Table of Contents

  1. Introduction
  2. Background and Related Work
  3. Proposed UVM-TLM Co-Simulation Framework
  4. Framework Architecture
  5. Key Modeling Aspects of vmodel
  6. Co-Simulation Verification Mechanism
  7. Integrated Verification and Evaluation Methodology
  8. Functional Verification Procedure
  9. Performance Evaluation Procedure
  10. Methodological Emphasis and Fidelity
  11. Results and Discussion
  12. Functional Verification Efficacy
  13. Performance Assessment and Simulation Efficiency
  14. Conclusion and Future Work

Figures (2)

  • Figure 1: Architecture of the UVM-TLM Co-Simulation Framework.
  • Figure 3: Functional verification flow using co-simulation.