Demonstration of low-overhead quantum error correction codes

TL;DR

This work demonstrates low-overhead quantum error correction using BB qLDPC codes on a 32-qubit superconducting processor with long-range connectivity. By embedding the $[[18,4,4]]$ BB code on a torus Tanner graph and a $[[18,6,3]]$ qLDPC code, the authors realize efficient syndrome extraction with weight-$6$ stabilizers and decode errors using a circuit-aware BP-OSD decoder, achieving logical error rates per cycle around $(8.9\pm0.2)\%$ and $(7.77\pm0.12)\%$, respectively. The experiment leverages multi-length tunable couplers, dynamical decoupling, and leakage rejection to mitigate errors, and shows that higher-distance BB/qLDPC codes can become advantageous as physical qubit performance improves. Overall, the results establish the feasibility of implementing diverse low-overhead qLDPC codes on superconducting processors and highlight the path toward scalable fault-tolerant quantum computing with improved encoding efficiency.

Abstract

Quantum computers hold the potential to surpass classical computers in solving complex computational problems. However, the fragility of quantum information and the error-prone nature of quantum operations make building large-scale, fault-tolerant quantum computers a prominent challenge. To combat errors, pioneering experiments have demonstrated a variety of quantum error correction codes. Yet, most of these codes suffer from low encoding efficiency, and their scalability is hindered by prohibitively high resource overheads. Here, we report the demonstration of two low-overhead quantum low-density parity-check (qLDPC) codes, a distance-4 bivariate bicycle code and a distance-3 qLDPC code, on our latest superconducting processor, Kunlun, featuring 32 long-range-coupled transmon qubits. Utilizing a two-dimensional architecture with overlapping long-range couplers, we demonstrate simultaneous measurements of all nonlocal weight-6 stabilizers via the periodic execution of an efficient syndrome extraction circuit. We achieve a logical error rate per logical qubit per cycle of $(8.91 \pm 0.17)\%$ for the distance-4 bivariate bicycle code with four logical qubits and $(7.77 \pm 0.12)\%$ for the distance-3 qLDPC code with six logical qubits. Our results establish the feasibility of implementing various qLDPC codes with long-range coupled superconducting processors, marking a crucial step towards large-scale low-overhead quantum error correction.

Figures (18)

• Figure 1: Implementation of the bivariate bicycle code.a, Schematic of the Kunlun processor. (Upper left) Tanner graph of the bivariate bicycle (BB) code embedded into a torus, where relevant sites are indexed by color-coded shapes and numbers. Only part of long-range connections are shown. (Lower left) Corresponding layout of the $32$-qubit superconducting quantum processor Kunlun that implements the $[[18,4,4]]$ BB code. The processor comprises $18$ data qubits (circles) categorized into $L$-type (blue) and $R$-type (orange), and $14$ check qubits (squares) for the $X$-type (red) and $Z$-type (green) stabilizer measurements. The purple lines highlight the couplers corresponding to the long-range connections in the Tanner graph. (Right) The $84$ couplers are grouped into four sets according to their lengths, and a crossing region between two interleaved couplers is magnified to reveal the underlying microstructure. b, Cumulative distributions of error probabilities measured on Kunlun. Blue: Pauli errors for parallel single-qubit gates; green: Pauli errors for parallel CZ gates; orange (purple): assignment errors for simultaneous two (three) -state measurements. Dashed vertical lines denote the mean values. c, Operation times of quantum operations in a single error correction cycle. The total cycle duration is 1895ns, including eight 30-ns single-qubit gate layers, seven 105-ns CZ gate layers, a 520-ns readout pulse, and a 400-ns photon ring-down time. The measurement of the data qubit in the last cycle is performed with an 890-ns readout pulse. d, Syndrome measurement circuit of the $[[18,4,4]]$ BB code. The data qubits (labeled $L^i$ and $R^i$) are initially prepared in product states. The first syndrome cycle of stabilizer measurements projects the data qubits into a logical state, and the subsequent cycles extract stabilizers for error correction. Each syndrome cycle contains seven layers of CZ gates interleaved with single-qubit gates to simultaneously extract $X$-type and $Z$-type stabilizers, and ends with the measurement of the $X$-type and $Z$-type check qubits (labeled $X^i$ and $Z^i$). In the final cycle, the data qubits are measured to obtain both stabilizer values and the information of the logical state. We insert additional Pauli $X$ and $Y$ gates between CZ layers and implement dynamical decoupling during the measurement of the check qubits to protect the data qubits from dephasing.
• Figure 1: Quantum circuit used to initialize and repeatedly error correct the six logical qubits of qLDPC code $\boldsymbol{[[18,6,3]]}$. The $X$-type checks and $Z$-type checks are marked with red and green colors, respectively. The data qubits of $L$ and $R$ type are marked with blue and orange colors, respectively.
• Figure 2: Stabilizer extraction and error detection in the bivariate bicycle code.a, A $Z$-type (green squares) or $X$-type (red squares) check qubit is coupled to six data qubits (circles), including three $L$-type (blue) and three $R$-type (orange), through both local and long-range couplers. b, Logical Pauli operators $\bar{Z}$ and $\bar{X}$ for the four logical qubits encoded in the distance-$4$ BB code. Each logical $\bar{Z}$ (green shaded) or $\bar{X}$ (red shaded) is the tensor product of the Pauli $Z$ or $X$ operators acting on specific sets of the data qubits. c, Quantum circuit for extracting a weight-six $X$-type or $Z$-type stabilizer. The circuit applies sequential CZ gates between the check qubit and each of the six data qubits. The Hadamard gates marked by red dashed squares are applied on the data qubits only when measuring the $X$-type stabilizer. Additional Pauli $X$ and $Y$ gates are inserted to mitigate qubit dephasing errors. d, Measured mean stabilizer values for the $14$ check qubits. For each stabilizer, the positive and negative bar heights correspond to averages over the $32$ basis states of even and odd parities, respectively. The overall averages across all $14$ stabilizers are indicated by green dashed lines, from which the average error can be calculated. e, Error detection probability over seven syndrome cycles for logical $Z$-basis and $X$-basis preservation experiments (more than $40,000$ experimental instances after leakage rejection). Dashed lines represent individual stabilizers and the solid line represents the average over all stabilizers. f, Similar to e, using a simulation based on the circuit-based depolarizing noise model.
• Figure 2: Detection probability for stabilizers over seven cycles for the qLDPC code with parameters $\boldsymbol{[[18,6,3]]}$. Each data point is obtained from over $40,000$ experimental instances. The dotted lines indicate the detection probability for each individual stabilizer, and the solid line shows the average detection probability across all stabilizers of the $Z$-type or $X$-type.
• Figure 3: Logical error rate per cycle and performance prediction.a and b, Logical error probability $P_L(t)$ (filled symbols: experiment; empty symbols: simulation) versus the number of executed cycles, for logical $Z$ basis state preservation and logical $X$ basis state preservation, respectively. Each individual data point represents more than $40,000$ experimental or simulated instances. Logical error probabilities for each of the four logical qubits are also shown. Solid line: fit to the experimental data from $t = 1$ to $6$; Dashed line: fit to the simulation. The fit is performed using the least-squares method on $\log(1- P_L(t))$ versus $t$. Lq, logical qubit; QEC, quantum error correction. c and d, Simulated logical error rate per cycle $p_L$ of bivariate bicycle codes, as functions of code distance and an error suppression factor $s$ on the current physical error rates exhibited in Fig. \ref{['fig:Fig1']}c, semilog plot. $s=1$ corresponds to the physical error rates in the current device.