SEGA-DCIM: Design Space Exploration-Guided Automatic Digital CIM Compiler with Multiple Precision Support

TL;DR

SEGA-DCIM tackles the challenge of manual, time-consuming DCIM design by providing an automatic, design-space exploration-guided compiler that supports multiple data precisions, including INT and FP. It combines a template-based DCIM generator with a MOGA-based explorer (NSGA-II) and a unified performance estimation model to automatically yield Pareto-front DCIM designs optimized for area, power, and delay. Key contributions include a synthesizable architecture supporting both INT and FP paths, a detailed cost model and optimization framework, and a workflow that generates final netlists and layouts using commercial tools. Experiments on a TSMC28 process show a wide design space and competitive efficiency relative to state-of-the-art DCIMs, while BF16 FP operations demonstrate favorable area-efficiency through pre-alignment. Overall, SEGA-DCIM reduces design time and increases the quality of DCIM solutions across diverse precision requirements.

Abstract

Digital computing-in-memory (DCIM) has been a popular solution for addressing the memory wall problem in recent years. However, the DCIM design still heavily relies on manual efforts, and the optimization of DCIM is often based on human experience. These disadvantages limit the time to market while increasing the design difficulty of DCIMs. This work proposes a design space exploration-guided automatic DCIM compiler (SEGA-DCIM) with multiple precision support, including integer and floating-point data precision operations. SEGA-DCIM can automatically generate netlists and layouts of DCIM designs by leveraging a template-based method. With a multi-objective genetic algorithm (MOGA)-based design space explorer, SEGA-DCIM can easily select appropriate DCIM designs for a specific application considering the trade-offs among area, power, and delay. As demonstrated by the experimental results, SEGA-DCIM offers solutions with wide design space, including integer and floating-point precision designs, while maintaining competitive performance compared to state-of-the-art (SOTA) DCIMs.

Figures (8)

• Figure 1: DCIM macro design trade-offs and various scenarios.
• Figure 2: DCIM for matrix-vector multiplication.
• Figure 3: The synthesizable DCIM architecture.
• Figure 4: Overview of SEGA-DCIM framework.
• Figure 5: Compute Unit design for Multiply-based DCIM.