Automated SAR ADC Sizing Using Analytical Equations

TL;DR

The paper addresses the time-intensive task of analog and mixed-signal circuit design by introducing an automated SAR ADC sizing workflow that maps high-level performance specifications directly to transistor sizing. It combines a dependency-graph representation of analytical equations to serialize simulations with a dual optimization scheme that couples system-level partitioning with subcircuit level Bayesian optimization. Two case studies demonstrate high SNDR with low power while satisfying all constraints, achieving competitive performance with minimal manual intervention. The approach reduces design effort and is extensible to other hierarchical AMS circuits, with future work focusing on relaxing the acyclic assumption, enabling offline sizing, and broadening applicability to additional circuit families.

Abstract

Conventional analog and mixed-signal (AMS) circuit designs heavily rely on manual effort, which is time-consuming and labor-intensive. This paper presents a fully automated design methodology for Successive Approximation Register (SAR) Analog-to-Digital Converters (ADCs) from performance specifications to complete transistor sizing. To tackle the high-dimensional sizing problem, we propose a dual optimization scheme. The system-level optimization iteratively partitions the overall requirements and analytically maps them to subcircuit design specifications, while local optimization loops determines the subcircuits' design parameters. The dependency graph-based framework serializes the simulations for verification, knowledge-based calculations, and transistor sizing optimization in topological order, which eliminates the need for human intervention. We demonstrate the effectiveness of the proposed methodology through two case studies with varying performance specifications, achieving high SNDR and low power consumption while meeting all the specified design constraints.

Figures (7)

• Figure 1: The Proposed Automated Design Framework
• Figure 2: A typical SAR ADC architecture, which is assumed in this work
• Figure 3: Circuit topologies of SAR ADC subcircuits
• Figure 4: Definition of $T_\text{pd}$: comparator propagation delay $(t2-t1)$
• Figure 5: Timing diagram of the clock signals