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GDNTT: an Area-Efficient Parallel NTT Accelerator Using Glitch-Driven Near-Memory Computing and Reconfigurable 10T SRAM

Hengyu Ding, Houran Ji, Jia Li, Jinhang Chen, Chin-Wing Sham, Yao Wang

TL;DR

The paper tackles the efficiency bottleneck of lattice-based post-quantum cryptography by presenting GDNTT, a glitch-driven near-memory NTT accelerator that combines a reconfigurable 10T SRAM with a glitch-based timing scheme to accelerate butterfly operations. The architecture integrates a top-level controller, glitch generator, dual SRAM arrays, and near-memory logic to enable efficient row/column data access and data mapping for NTT/INTT computations, leveraging Cooley–Tukey and Gentleman–Sande algorithms. Key innovations include the 10T SRAM bit-cell design for precise operand pairing, near-memory computation for modular operations, and a glitch-driven control mechanism that reduces latency and enables multi-step execution within a single clock cycle. Experimental results in 28 nm show 67.1 kNTT/s at 256-point with 0.006 mm$^2$ area and throughput-per-area up to 1.5–28× higher than state-of-the-art, signaling strong potential for energy-efficient PQC on edge devices.

Abstract

With the rapid advancement of quantum computing technology, post-quantum cryptography (PQC) has emerged as a pivotal direction for next-generation encryption standards. Among these, lattice-based cryptographic schemes rely heavily on the fast Number Theoretic Transform (NTT) over polynomial rings, whose performance directly determines encryption/decryption throughput and energy efficiency. However, existing software-based NTT implementations struggle to meet the real-time performance and low-power requirements of IoT and edge devices. To address this challenge, this paper proposes an area-efficient highly parallel NTT accelerator with glitch-driven near-memory computing (GDNTT). The design integrates a 10T SRAM for data storage, enabling flexible row/column data access and streamlining circuit mapping strategies. Furthermore, a glitch generator is incorporated into the near-memory computing unit, significantly reducing the latency of butterfly operations. Evaluation results show that the proposed NTT accelerator achieves a 1.5~28* improvement in throughput-per-area compared to the state-of-the-art.

GDNTT: an Area-Efficient Parallel NTT Accelerator Using Glitch-Driven Near-Memory Computing and Reconfigurable 10T SRAM

TL;DR

The paper tackles the efficiency bottleneck of lattice-based post-quantum cryptography by presenting GDNTT, a glitch-driven near-memory NTT accelerator that combines a reconfigurable 10T SRAM with a glitch-based timing scheme to accelerate butterfly operations. The architecture integrates a top-level controller, glitch generator, dual SRAM arrays, and near-memory logic to enable efficient row/column data access and data mapping for NTT/INTT computations, leveraging Cooley–Tukey and Gentleman–Sande algorithms. Key innovations include the 10T SRAM bit-cell design for precise operand pairing, near-memory computation for modular operations, and a glitch-driven control mechanism that reduces latency and enables multi-step execution within a single clock cycle. Experimental results in 28 nm show 67.1 kNTT/s at 256-point with 0.006 mm area and throughput-per-area up to 1.5–28× higher than state-of-the-art, signaling strong potential for energy-efficient PQC on edge devices.

Abstract

With the rapid advancement of quantum computing technology, post-quantum cryptography (PQC) has emerged as a pivotal direction for next-generation encryption standards. Among these, lattice-based cryptographic schemes rely heavily on the fast Number Theoretic Transform (NTT) over polynomial rings, whose performance directly determines encryption/decryption throughput and energy efficiency. However, existing software-based NTT implementations struggle to meet the real-time performance and low-power requirements of IoT and edge devices. To address this challenge, this paper proposes an area-efficient highly parallel NTT accelerator with glitch-driven near-memory computing (GDNTT). The design integrates a 10T SRAM for data storage, enabling flexible row/column data access and streamlining circuit mapping strategies. Furthermore, a glitch generator is incorporated into the near-memory computing unit, significantly reducing the latency of butterfly operations. Evaluation results show that the proposed NTT accelerator achieves a 1.5~28* improvement in throughput-per-area compared to the state-of-the-art.
Paper Structure (9 sections, 2 equations, 3 figures, 1 table, 2 algorithms)

This paper contains 9 sections, 2 equations, 3 figures, 1 table, 2 algorithms.

Table of Contents

  1. Introduction
  2. Background
  3. Proposed Architecture
  4. Overall Architecture
  5. Design of 10T SRAM and Parallel Memory Access Scheme
  6. Near-Memory Computation
  7. Glitch-driven High-speed Butterfly Operation
  8. Results and Discussion
  9. Conclusion

Figures (3)

  • Figure 1: (a) Overall architecture of the proposed NTT accelerator. (b) Detailed structure of the near-memory computation unit. (c) Structure of the proposed 10T SRAM bit-cell. (d) Structure of the basic arithmetic module.
  • Figure 2: Detailed NTT caculation flow.
  • Figure 3: Schematic of the glitch generator and critical timing waveforms for NTT operations.