Regular mixed-radix DFT matrix factorization for in-place FFT accelerators

TL;DR

The paper addresses the challenge of implementing efficient, in-place FFT accelerators with a fixed datapath that can handle arbitrary FFT lengths and support both DIT and DIF. It introduces a regular mixed-radix factorization of the DFT matrix, coherent with memory-based architectures, and provides correction proofs and index-handling techniques to enable runtime reconfiguration via address generators. Core contributions include a rigorous FFT splitting rule, multi-index indexing and index inversion theory, and explicit DIT and DIF factorization formulas with stage-wise operators mapped to hardware, facilitating conflict-free, high-throughput execution. The proposed framework unifies DIT and DIF within a single architectural template, enabling runtime selection of FFT length and decimation type, and offers pathways to extend beyond 1r1w SRAM to broader memory architectures and self-sorting FFT. This work thus provides both theoretical foundations and practical guidelines for designing flexible, high-throughput, memory-based FFT accelerators with provable correctness.

Abstract

The generic vector memory based accelerator is considered which supports DIT and DIF FFT with fixed datapath. The regular mixed-radix factorization of the DFT matrix coherent with the accelerator architecture is proposed and the correction proof is presented. It allows better understanding of architecture requirements and simplifies the developing and proving correctness of more complicated algorithms and conflict-free addressing schemes.

Figures (1)

• Figure 1: Architecture of FFT IP 1r1w RAM.

Theorems & Definitions (21)

• Lemma 1
• proof
• Lemma 2
• proof
• Lemma 3
• proof
• Corollary 1
• proof
• Definition 1
• Lemma 4