Modeling PFAS in Semiconductor Manufacturing to Quantify Trade-offs in Energy Efficiency and Environmental Impact of Computing Systems

TL;DR

This work addresses the environmental and health concerns of PFAS used in semiconductor manufacturing by proposing a PFAS-aware design framework that quantifies PFAS consumption at the IC design phase. The framework couples a PFAS analytical model of lithography and metal-stack complexity with an architectural carbon tool (ACT) to enable joint PFAS–carbon trade-offs, and validates the approach with case studies on PFAS-aware design. Key findings show that EUV lithography at 7 nm can reduce PFAS by $18\%$ and improve power-performance-area relative to DUV, while BEOL metal-layer reductions can yield up to $3\times$ PFAS reductions with minimal PPA penalties; at the SoC level, BEOL optimization can achieve about $1.58\times$ PFAS reduction with small area overhead. The work emphasizes design-time optimization, standardized PFAS quantification, and the potential of chiplet approaches to further reduce PFAS, highlighting significant practical impact for sustainable computing.

Abstract

The electronics and semiconductor industry is a prominent consumer of per- and poly-fluoroalkyl substances (PFAS), also known as forever chemicals. PFAS are persistent in the environment and can bioaccumulate to ecological and human toxic levels. Computer designers have an opportunity to reduce the use of PFAS in semiconductors and electronics manufacturing, including integrated circuits (IC), batteries, displays, etc., which currently account for a staggering 10% of the total PFAS fluoropolymers usage in Europe alone. In this paper, we present a framework where we (1) quantify the environmental impact of PFAS in computing systems manufacturing with granular consideration of the metal layer stack and patterning complexities in IC manufacturing at the design phase, (2) identify contending trends between embodied carbon (carbon footprint due to hardware manufacturing) versus PFAS. For example, manufacturing an IC at a 7 nm technology node using EUV lithography uses 18% less PFAS-containing layers, compared to manufacturing the same IC at a 7 nm technology node using DUV immersion lithography (instead of EUV) unlike embodied carbon trends, and (3) conduct case studies to illustrate how to optimize and trade-off designs with lower PFAS, while meeting power-performance-area constraints. We show that optimizing designs to use less back-end-of-line (BEOL) metal stack layers can save 1.7$\times$ PFAS-containing layers in systolic arrays.

Figures (12)

• Figure 1: Electronic and semiconductor industries are the third largest consumer of fluoropolymers across sectors in Europe in 2020 (left) fluoropolymer2020EUelectronics. In Europe alone, over 4.21 kilotons of PFAS were used in semiconductors and electronics manufacturing (right) PFAsNature2023article. Computer designers and researchers need to identify and incorporate design optimizations to reduce PFAS at the design phase.
• Figure 2: There are three possible contaminant streams for PFAS in semiconductors and electronics: most commonly atmospheric and aqueous releases throughout manufacturing, and leachate release through the soil due to e-waste that contaminates the environment in the long-term.
• Figure 3: Majority of PFAS used in semiconductor manufacturing are either incinerated or go to wastewater SIA2024PFASpaper, signifying major opportunities to reduce PFAS.
• Figure 4: Lithography is a key fundamental technology for semiconductor manufacturing. A PFAS-containing layer in lithography includes chemicals, such as bottom and top antireflective coats, photoresist and topcoat. We illustrate example process complexities for immersion 193 nm DUV (ArFi) and EUV industry-wide lithography options such as LE-$N$, SADP and SAQP. $N$ indicates number of litho-etch sequences, ranging from single to quadruple patterning.
• Figure 5: Number of PFAS-containing lithography layers in chip manufacturing across process technology nodes, based on our PFAS model. PFAS used in manufacturing are dependent on the design's BEOL metal stack and patterning complexity. Unlike energy consumption and carbon footprint, PFAS do not exhibit consistent upward trends with more advanced technology nodes.