Extend IVerilog to Support Batch RTL Fault Simulation

TL;DR

The paper addresses the bottleneck of RTL fault simulation in functional safety workflows. It extends IVerilog with a batch fault simulation framework by fusing event-driven simulation and a concurrent fault-simulation algorithm, enabling simultaneous fault propagation across the RTL netlist and behavioral blocks. The method includes a five-step RTL-netlist fault pipeline, per-fault instances for behavioral descriptions, and a case study illustrating fault visibility and propagation. Experiments compare against Verilator-Fsim and Z01X, and an open-source RTL fault simulator, showing speedups of up to around 3.4x against IVerilog-Fsim and 2.2x against Z01X. The results suggest that batch, event-driven fault simulation in IVerilog offers practical scalability benefits for functional-safety-oriented RTL verification.

Abstract

The advancement of functional safety has made RTL-level fault simulation increasingly important to achieve iterative efficiency in the early stages of design and to ensure compliance with functional safety standards. In this paper, we extend IVerilog to support batch RTL fault simulation and integrate the event-driven algorithm and the concurrent fault simulation algorithm. Comparative experiments with a state-of-the-art commercial simulator and an open-source RTL fault simulator demonstrate that our simulator achieves a performance improvement of 2.2$\times$ and 3.4$\times$, respectively.

Figures (1)

• Figure 1: Concurrent fault simulation on the RTL.