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RTOS Architectures that Solve the Diminishing Bandwidth Problem

Mazen Arakji

TL;DR

The paper tackles the Diminishing Bandwidth Problem in RTOSes, where interrupt-disable periods scale with task count and threaten peripheral bandwidth. It proposes three RTOS architectures—the Defer Structure, Barriers and Requests, and Strictly Atomic—and two hardware solutions to ensure the highest-priority task can always receive input within deadlines. Each architecture offers different defer structures, readiness list strategies, and atomicity mechanisms to minimize latency while preserving correctness, with Barriers and Requests (Unsorted Ready List) highlighted as optimal. The work emphasizes extensibility, predictable timing, and practical deployment in embedded systems, including considerations for multi-core implementations and hardware-assisted approaches.

Abstract

The Diminishing Bandwidth Problem is a long standing, previously unidentified, extensibility problem of current real-time operating systems characterized by a superficial dependency between the number of tasks in a system and the maximum bandwidth associated with a peripheral device. In the worst case, this diabolical deficiency will continue to decrease the maximum bandwidth of a peripheral device as more tasks are added to the application. If this is not taken into account, a previously functional application may experience data loss if more tasks are added to it in order to, for example, implement new features. Three novel RTOS architectures that solve the Diminishing Bandwidth Problem are specified and discussed: the Defer Structure RTOS Architecture, the Barriers and Requests RTOS Architecture, and the Strictly Atomic RTOS Architecture. Finally, two hardware solutions to the Diminishing Bandwidth Problem are also presented.

RTOS Architectures that Solve the Diminishing Bandwidth Problem

TL;DR

The paper tackles the Diminishing Bandwidth Problem in RTOSes, where interrupt-disable periods scale with task count and threaten peripheral bandwidth. It proposes three RTOS architectures—the Defer Structure, Barriers and Requests, and Strictly Atomic—and two hardware solutions to ensure the highest-priority task can always receive input within deadlines. Each architecture offers different defer structures, readiness list strategies, and atomicity mechanisms to minimize latency while preserving correctness, with Barriers and Requests (Unsorted Ready List) highlighted as optimal. The work emphasizes extensibility, predictable timing, and practical deployment in embedded systems, including considerations for multi-core implementations and hardware-assisted approaches.

Abstract

The Diminishing Bandwidth Problem is a long standing, previously unidentified, extensibility problem of current real-time operating systems characterized by a superficial dependency between the number of tasks in a system and the maximum bandwidth associated with a peripheral device. In the worst case, this diabolical deficiency will continue to decrease the maximum bandwidth of a peripheral device as more tasks are added to the application. If this is not taken into account, a previously functional application may experience data loss if more tasks are added to it in order to, for example, implement new features. Three novel RTOS architectures that solve the Diminishing Bandwidth Problem are specified and discussed: the Defer Structure RTOS Architecture, the Barriers and Requests RTOS Architecture, and the Strictly Atomic RTOS Architecture. Finally, two hardware solutions to the Diminishing Bandwidth Problem are also presented.
Paper Structure (15 sections, 17 figures, 1 table)

This paper contains 15 sections, 17 figures, 1 table.

Table of Contents

  1. Introduction
  2. Background
  3. THE DEFERRED STRUCTURE RTOS ARCHITECTURE
  4. FIFO Semaphore Counts Buffer
  5. FIFO Semaphore Buffer
  6. FIFO Linked List
  7. Bitmap Flags
  8. THE BARRIERS AND REQUESTS RTOS ARCHITECTURE
  9. Sorted Ready List - Atomic Insertion Algorithm
  10. Unsorted Ready List
  11. THE STRICTLY ATOMIC RTOS ARCHITECTURE
  12. HARDWARE SOLUTIONS TO THE DIMINISHING BANDWIDTH PROBLEM
  13. Without DMA Controller
  14. New DMA Controller Design
  15. Conclusions

Figures (17)

  • Figure 1: Current RTOS Interrupt Handler
  • Figure 2: LOAD/STORE Exclusive Functions
  • Figure 3: Atomic Instructions to Insert into FIFO Buffer
  • Figure 4: FIFO Semaphore Counts Buffer Interrupt Handler - smphrGvIsr() only
  • Figure 5: FIFO Semaphore Counts Buffer - Task Blocking Self or Unblocking other Task
  • ...and 12 more figures